Unverified Commit 62de5356 authored by Jernej Skrabec's avatar Jernej Skrabec Committed by Maxime Ripard
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ARM: dts: sun8i: r40: Add deinterlace node 



R40 contains deinterlace core compatible to that in H3. One peculiarity
is that RAM gate is shared with CSI1. User manual states it's separate
but that's not true. Shared gate was verified with BSP Linux code check
and with runtime tests (CPU crashed if CSI1 gate was not ungated).

Signed-off-by: default avatarJernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: default avatarMaxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20210106181901.1324075-3-jernej.skrabec@siol.net
parent 3069a84f

arch/arm/boot/dts/sun8i-r40.dtsi

+19 −0
Original line number Diff line number Diff line
@@ -190,6 +190,25 @@ 
			};

		};



		deinterlace: deinterlace@1400000 {

			compatible = "allwinner,sun8i-r40-deinterlace",

				     "allwinner,sun8i-h3-deinterlace";

			reg = <0x01400000 0x20000>;

			clocks = <&ccu CLK_BUS_DEINTERLACE>,

				 <&ccu CLK_DEINTERLACE>,

				 /*

				  * NOTE: Contrary to what datasheet claims,

				  * DRAM deinterlace gate doesn't exist and

				  * it's shared with CSI1.

				  */

				 <&ccu CLK_DRAM_CSI1>;

			clock-names = "bus", "mod", "ram";

			resets = <&ccu RST_BUS_DEINTERLACE>;

			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;

			interconnects = <&mbus 9>;

			interconnect-names = "dma-mem";

		};



		syscon: system-control@1c00000 {

			compatible = "allwinner,sun8i-r40-system-control",

				     "allwinner,sun4i-a10-system-control";