Commit 627e66f2 authored by Michael Ellerman's avatar Michael Ellerman
Browse files

Merge changes from Paul Gortmaker 

Merge the changes to retire the legacy WR sbc8548 and sbc8641 platforms
from Paul. These were sent as a pull request, but I rebased them onto
rc2 so as not to pull too many unrelated changes in to my next.

Description from Paul's pull request follows:

In v2.6.27 (2008, 917f0af9) the sbc8260 support was implicitly
retired by not being carried forward through the ppc --> powerpc
device tree transition.

Then, in v3.6 (2012, b048b4e1) we retired the support for the
sbc8560 boards.

Next, in v4.18 (2017, 3bc6cf5a) we retired the support for the
2006 vintage sbc834x boards.

The sbc8548 and sbc8641d boards were maybe 1-2 years newer than the
sbc834x boards, but it is also 3+ years later, so it makes sense to
now retire them as well - which is what is done here.

These two remaining WR boards were based on the Freescale MPC8548-CDS
and the MPC8641D-HPCN reference board implementations.  Having had the
chance to use these and many other Fsl ref boards, I know this:  The
Freescale reference boards were typically produced in limited quantity
and primarily available to BSP developers and hardware designers, and
not likely to have found a 2nd life with hobbyists and/or collectors.

It was good to have that BSP code subjected to mainline review and
hence also widely available back in the day. But given the above, we
should probably also be giving serious consideration to retiring
additional similar age/type reference board platforms as well.

I've always felt it is important for us to be proactive in retiring
old code, since it has a genuine non-zero carrying cost, as described
in the 930d52c0 merge log.  But for the here and now, we just
clean up the remaining BSP code that I had added for SBC platforms.

Link: https://lore.kernel.org/r/20210824174209.GB160508@windriver.com
parents 465e333e 5bd4ae07

MAINTAINERS

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@@ -6801,7 +6801,6 @@ F: Documentation/admin-guide/media/em28xx* 
F:	drivers/media/usb/em28xx/









EMBEDDED LINUX









M:	Paul Gortmaker <paul.gortmaker@windriver.com>









M:	Matt Mackall <mpm@selenic.com>









M:	David Woodhouse <dwmw2@infradead.org>









L:	linux-embedded@vger.kernel.org
































arch/powerpc/boot/Makefile



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−1






























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@@ -341,7 +341,6 @@ image-$(CONFIG_TQM8541)			+= cuImage.tqm8541







image-$(CONFIG_TQM8548)			+= cuImage.tqm8548









image-$(CONFIG_TQM8555)			+= cuImage.tqm8555









image-$(CONFIG_TQM8560)			+= cuImage.tqm8560









image-$(CONFIG_SBC8548)			+= cuImage.sbc8548









image-$(CONFIG_KSI8560)			+= cuImage.ksi8560



















# Board ports in arch/powerpc/platform/86xx/Kconfig
































arch/powerpc/boot/dts/fsl/sbc8641d.dts
deleted100644 → 0



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// SPDX-License-Identifier: GPL-2.0-or-later









/*









 * SBC8641D Device Tree Source









 *









 * Copyright 2008 Wind River Systems Inc.









 *









 * Paul Gortmaker (see MAINTAINERS for contact information)









 *









 * Based largely on the mpc8641_hpcn.dts by Freescale Semiconductor Inc.









 */



















/include/ "mpc8641si-pre.dtsi"



















/ {









	model = "SBC8641D";









	compatible = "wind,sbc8641";



















	memory {









		device_type = "memory";









		reg = <0x00000000 0x20000000>;	// 512M at 0x0









	};



















	lbc: localbus@f8005000 {









		reg = <0xf8005000 0x1000>;



















		ranges = <0 0 0xff000000 0x01000000	// 16MB Boot flash









			  1 0 0xf0000000 0x00010000	// 64KB EEPROM









			  2 0 0xf1000000 0x00100000	// EPLD (1MB)









			  3 0 0xe0000000 0x04000000	// 64MB LB SDRAM (CS3)









			  4 0 0xe4000000 0x04000000	// 64MB LB SDRAM (CS4)









			  6 0 0xf4000000 0x00100000	// LCD display (1MB)









			  7 0 0xe8000000 0x04000000>;	// 64MB OneNAND



















		flash@0,0 {









			compatible = "cfi-flash";









			reg = <0 0 0x01000000>;









			bank-width = <2>;









			device-width = <2>;









			#address-cells = <1>;









			#size-cells = <1>;









			partition@0 {









				label = "dtb";









				reg = <0x00000000 0x00100000>;









				read-only;









			};









			partition@300000 {









				label = "kernel";









				reg = <0x00100000 0x00400000>;









				read-only;









			};









			partition@400000 {









				label = "fs";









				reg = <0x00500000 0x00a00000>;









			};









			partition@700000 {









				label = "firmware";









				reg = <0x00f00000 0x00100000>;









				read-only;









			};









		};



















		epld@2,0 {









			compatible = "wrs,epld-localbus";









			#address-cells = <2>;









			#size-cells = <1>;









			reg = <2 0 0x100000>;









			ranges = <0 0 5 0 1	// User switches









				  1 0 5 1 1	// Board ID/Rev









				  3 0 5 3 1>;	// LEDs









		};









	};



















	soc: soc@f8000000 {









		ranges = <0x00000000 0xf8000000 0x00100000>;



















		enet0: ethernet@24000 {









			tbi-handle = <&tbi0>;









			phy-handle = <&phy0>;









			phy-connection-type = "rgmii-id";









		};



















		mdio@24520 {









			phy0: ethernet-phy@1f {









				reg = <0x1f>;









			};









			phy1: ethernet-phy@0 {









				reg = <0>;









			};









			phy2: ethernet-phy@1 {









				reg = <1>;









			};









			phy3: ethernet-phy@2 {









				reg = <2>;









			};









			tbi0: tbi-phy@11 {









				reg = <0x11>;









				device_type = "tbi-phy";









			};









		};



















		enet1: ethernet@25000 {









			tbi-handle = <&tbi1>;









			phy-handle = <&phy1>;









			phy-connection-type = "rgmii-id";









		};



















		mdio@25520 {









			tbi1: tbi-phy@11 {









				reg = <0x11>;









				device_type = "tbi-phy";









			};









		};



















		enet2: ethernet@26000 {









			tbi-handle = <&tbi2>;









			phy-handle = <&phy2>;









			phy-connection-type = "rgmii-id";









		};



















		mdio@26520 {









			tbi2: tbi-phy@11 {









				reg = <0x11>;









				device_type = "tbi-phy";









			};









		};



















		enet3: ethernet@27000 {









			tbi-handle = <&tbi3>;









			phy-handle = <&phy3>;









			phy-connection-type = "rgmii-id";









		};



















		mdio@27520 {









			tbi3: tbi-phy@11 {









				reg = <0x11>;









				device_type = "tbi-phy";









			};









		};









	};



















	pci0: pcie@f8008000 {









		reg = <0xf8008000 0x1000>;









		ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000









			  0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;









		interrupt-map-mask = <0xff00 0 0 7>;



















		pcie@0 {









			ranges = <0x02000000 0x0 0x80000000









				  0x02000000 0x0 0x80000000









				  0x0 0x20000000



















				  0x01000000 0x0 0x00000000









				  0x01000000 0x0 0x00000000









				  0x0 0x00100000>;









		};



















	};



















	pci1: pcie@f8009000 {









		reg = <0xf8009000 0x1000>;









		ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000









			  0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;



















		pcie@0 {









			ranges = <0x02000000 0x0 0xa0000000









				  0x02000000 0x0 0xa0000000









				  0x0 0x20000000



















				  0x01000000 0x0 0x00000000









				  0x01000000 0x0 0x00000000









				  0x0 0x00100000>;









		};









	};









};



















/include/ "mpc8641si-post.dtsi"
























arch/powerpc/boot/dts/sbc8548-altflash.dts
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// SPDX-License-Identifier: GPL-2.0-or-later









/*









 * SBC8548 Device Tree Source









 *









 * Configured for booting off the alternate (64MB SODIMM) flash.









 * Requires switching JP12 jumpers and changing SW2.8 setting.









 *









 * Copyright 2013 Wind River Systems Inc.









 *









 * Paul Gortmaker (see MAINTAINERS for contact information)









 */





























/dts-v1/;



















/include/ "sbc8548-pre.dtsi"



















/{









	localbus@e0000000 {









		#address-cells = <2>;









		#size-cells = <1>;









		compatible = "simple-bus";









		reg = <0xe0000000 0x5000>;









		interrupt-parent = <&mpic>;



















		ranges = <0x0 0x0 0xfc000000 0x04000000		/*64MB Flash*/









			  0x3 0x0 0xf0000000 0x04000000		/*64MB SDRAM*/









			  0x4 0x0 0xf4000000 0x04000000 	/*64MB SDRAM*/









			  0x5 0x0 0xf8000000 0x00b10000		/* EPLD */









			  0x6 0x0 0xef800000 0x00800000>;	/*8MB Flash*/



















		flash@0,0 {









			#address-cells = <1>;









			#size-cells = <1>;









			reg = <0x0 0x0 0x04000000>;









			compatible = "intel,JS28F128", "cfi-flash";









			bank-width = <4>;









			device-width = <1>;









			partition@0 {









				label = "space";









				/* FC000000 -> FFEFFFFF */









				reg = <0x00000000 0x03f00000>;









			};









			partition@3f00000 {









				label = "bootloader";









				/* FFF00000 -> FFFFFFFF */









				reg = <0x03f00000 0x00100000>;









				read-only;









			};









                };





























		epld@5,0 {









			compatible = "wrs,epld-localbus";









			#address-cells = <2>;









			#size-cells = <1>;









			reg = <0x5 0x0 0x00b10000>;









			ranges = <









				0x0 0x0 0x5 0x000000 0x1fff	/* LED */









				0x1 0x0 0x5 0x100000 0x1fff	/* Switches */









				0x3 0x0 0x5 0x300000 0x1fff	/* HW Rev. */









				0xb 0x0	0x5 0xb00000 0x1fff	/* EEPROM */









			>;



















			led@0,0 {









				compatible = "led";









				reg = <0x0 0x0 0x1fff>;









			};



















			switches@1,0 {









				compatible = "switches";









				reg = <0x1 0x0 0x1fff>;









			};



















			hw-rev@3,0 {









				compatible = "hw-rev";









				reg = <0x3 0x0 0x1fff>;









			};



















			eeprom@b,0 {









				compatible = "eeprom";









				reg = <0xb 0 0x1fff>;









			};



















		};



















		alt-flash@6,0 {









			#address-cells = <1>;









			#size-cells = <1>;









			compatible = "intel,JS28F640", "cfi-flash";









			reg = <0x6 0x0 0x800000>;









			bank-width = <1>;









			device-width = <1>;









			partition@0 {









				label = "space";









				/* EF800000 -> EFF9FFFF */









				reg = <0x00000000 0x007a0000>;









			};









			partition@7a0000 {









				label = "bootloader";









				/* EFFA0000 -> EFFFFFFF */









				reg = <0x007a0000 0x00060000>;









				read-only;









			};









		};





























        };









};



















/include/ "sbc8548-post.dtsi"
























arch/powerpc/boot/dts/sbc8548-post.dtsi
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// SPDX-License-Identifier: GPL-2.0-or-later









/*









 * SBC8548 Device Tree Source









 *









 * Copyright 2007 Wind River Systems Inc.









 *









 * Paul Gortmaker (see MAINTAINERS for contact information)









 */



















/{









	soc8548@e0000000 {









		#address-cells = <1>;









		#size-cells = <1>;









		device_type = "soc";









		ranges = <0x00000000 0xe0000000 0x00100000>;









		bus-frequency = <0>;









		compatible = "simple-bus";



















		ecm-law@0 {









			compatible = "fsl,ecm-law";









			reg = <0x0 0x1000>;









			fsl,num-laws = <10>;









		};



















		ecm@1000 {









			compatible = "fsl,mpc8548-ecm", "fsl,ecm";









			reg = <0x1000 0x1000>;









			interrupts = <17 2>;









			interrupt-parent = <&mpic>;









		};



















		memory-controller@2000 {









			compatible = "fsl,mpc8548-memory-controller";









			reg = <0x2000 0x1000>;









			interrupt-parent = <&mpic>;









			interrupts = <0x12 0x2>;









		};



















		L2: l2-cache-controller@20000 {









			compatible = "fsl,mpc8548-l2-cache-controller";









			reg = <0x20000 0x1000>;









			cache-line-size = <0x20>;	// 32 bytes









			cache-size = <0x80000>;	// L2, 512K









			interrupt-parent = <&mpic>;









			interrupts = <0x10 0x2>;









		};



















		i2c@3000 {









			#address-cells = <1>;









			#size-cells = <0>;









			cell-index = <0>;









			compatible = "fsl-i2c";









			reg = <0x3000 0x100>;









			interrupts = <0x2b 0x2>;









			interrupt-parent = <&mpic>;









			dfsrr;









		};



















		i2c@3100 {









			#address-cells = <1>;









			#size-cells = <0>;









			cell-index = <1>;









			compatible = "fsl-i2c";









			reg = <0x3100 0x100>;









			interrupts = <0x2b 0x2>;









			interrupt-parent = <&mpic>;









			dfsrr;









		};



















		dma@21300 {









			#address-cells = <1>;









			#size-cells = <1>;









			compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";









			reg = <0x21300 0x4>;









			ranges = <0x0 0x21100 0x200>;









			cell-index = <0>;









			dma-channel@0 {









				compatible = "fsl,mpc8548-dma-channel",









						"fsl,eloplus-dma-channel";









				reg = <0x0 0x80>;









				cell-index = <0>;









				interrupt-parent = <&mpic>;









				interrupts = <20 2>;









			};









			dma-channel@80 {









				compatible = "fsl,mpc8548-dma-channel",









						"fsl,eloplus-dma-channel";









				reg = <0x80 0x80>;









				cell-index = <1>;









				interrupt-parent = <&mpic>;









				interrupts = <21 2>;









			};









			dma-channel@100 {









				compatible = "fsl,mpc8548-dma-channel",









						"fsl,eloplus-dma-channel";









				reg = <0x100 0x80>;









				cell-index = <2>;









				interrupt-parent = <&mpic>;









				interrupts = <22 2>;









			};









			dma-channel@180 {









				compatible = "fsl,mpc8548-dma-channel",









						"fsl,eloplus-dma-channel";









				reg = <0x180 0x80>;









				cell-index = <3>;









				interrupt-parent = <&mpic>;









				interrupts = <23 2>;









			};









		};



















		enet0: ethernet@24000 {









			#address-cells = <1>;









			#size-cells = <1>;









			cell-index = <0>;









			device_type = "network";









			model = "eTSEC";









			compatible = "gianfar";









			reg = <0x24000 0x1000>;









			ranges = <0x0 0x24000 0x1000>;









			local-mac-address = [ 00 00 00 00 00 00 ];









			interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;









			interrupt-parent = <&mpic>;









			tbi-handle = <&tbi0>;









			phy-handle = <&phy0>;



















			mdio@520 {









				#address-cells = <1>;









				#size-cells = <0>;









				compatible = "fsl,gianfar-mdio";









				reg = <0x520 0x20>;



















				phy0: ethernet-phy@19 {









					interrupt-parent = <&mpic>;









					interrupts = <0x6 0x1>;









					reg = <0x19>;









				};









				phy1: ethernet-phy@1a {









					interrupt-parent = <&mpic>;









					interrupts = <0x7 0x1>;









					reg = <0x1a>;









				};









				tbi0: tbi-phy@11 {









					reg = <0x11>;









					device_type = "tbi-phy";









				};









			};









		};



















		enet1: ethernet@25000 {









			#address-cells = <1>;









			#size-cells = <1>;









			cell-index = <1>;









			device_type = "network";









			model = "eTSEC";









			compatible = "gianfar";









			reg = <0x25000 0x1000>;









			ranges = <0x0 0x25000 0x1000>;









			local-mac-address = [ 00 00 00 00 00 00 ];









			interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>;









			interrupt-parent = <&mpic>;









			tbi-handle = <&tbi1>;









			phy-handle = <&phy1>;



















			mdio@520 {









				#address-cells = <1>;









				#size-cells = <0>;









				compatible = "fsl,gianfar-tbi";









				reg = <0x520 0x20>;



















				tbi1: tbi-phy@11 {









					reg = <0x11>;









					device_type = "tbi-phy";









				};









			};









		};



















		serial0: serial@4500 {









			cell-index = <0>;









			device_type = "serial";









			compatible = "fsl,ns16550", "ns16550";









			reg = <0x4500 0x100>;	// reg base, size









			clock-frequency = <0>;	// should we fill in in uboot?









			interrupts = <0x2a 0x2>;









			interrupt-parent = <&mpic>;









		};



















		serial1: serial@4600 {









			cell-index = <1>;









			device_type = "serial";









			compatible = "fsl,ns16550", "ns16550";









			reg = <0x4600 0x100>;	// reg base, size









			clock-frequency = <0>;	// should we fill in in uboot?









			interrupts = <0x2a 0x2>;









			interrupt-parent = <&mpic>;









		};



















		global-utilities@e0000 {	//global utilities reg









			compatible = "fsl,mpc8548-guts";









			reg = <0xe0000 0x1000>;









			fsl,has-rstcr;









		};



















		crypto@30000 {









			compatible = "fsl,sec2.1", "fsl,sec2.0";









			reg = <0x30000 0x10000>;









			interrupts = <45 2>;









			interrupt-parent = <&mpic>;









			fsl,num-channels = <4>;









			fsl,channel-fifo-len = <24>;









			fsl,exec-units-mask = <0xfe>;









			fsl,descriptor-types-mask = <0x12b0ebf>;









		};



















		mpic: pic@40000 {









			interrupt-controller;









			#address-cells = <0>;









			#interrupt-cells = <2>;









			reg = <0x40000 0x40000>;









			compatible = "chrp,open-pic";









			device_type = "open-pic";









		};









	};



















	pci0: pci@e0008000 {









		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;









		interrupt-map = <









			/* IDSEL 0x01 (PCI-X slot) @66MHz */









			0x0800 0x0 0x0 0x1 &mpic 0x2 0x1









			0x0800 0x0 0x0 0x2 &mpic 0x3 0x1









			0x0800 0x0 0x0 0x3 &mpic 0x4 0x1









			0x0800 0x0 0x0 0x4 &mpic 0x1 0x1



















			/* IDSEL 0x11 (PCI, 3.3V 32bit) @33MHz */









			0x8800 0x0 0x0 0x1 &mpic 0x2 0x1









			0x8800 0x0 0x0 0x2 &mpic 0x3 0x1









			0x8800 0x0 0x0 0x3 &mpic 0x4 0x1









			0x8800 0x0 0x0 0x4 &mpic 0x1 0x1>;



















		interrupt-parent = <&mpic>;









		interrupts = <0x18 0x2>;









		bus-range = <0 0>;









		ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000









			  0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00800000>;









		clock-frequency = <66000000>;









		#interrupt-cells = <1>;









		#size-cells = <2>;









		#address-cells = <3>;









		reg = <0xe0008000 0x1000>;









		compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";









		device_type = "pci";









	};



















	pci1: pcie@e000a000 {









		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;









		interrupt-map = <



















			/* IDSEL 0x0 (PEX) */









			0x0000 0x0 0x0 0x1 &mpic 0x0 0x1









			0x0000 0x0 0x0 0x2 &mpic 0x1 0x1









			0x0000 0x0 0x0 0x3 &mpic 0x2 0x1









			0x0000 0x0 0x0 0x4 &mpic 0x3 0x1>;



















		interrupt-parent = <&mpic>;









		interrupts = <0x1a 0x2>;









		bus-range = <0x0 0xff>;









		ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000









			  0x01000000 0x0 0x00000000 0xe2800000 0x0 0x08000000>;









		clock-frequency = <33000000>;









		#interrupt-cells = <1>;









		#size-cells = <2>;









		#address-cells = <3>;









		reg = <0xe000a000 0x1000>;









		compatible = "fsl,mpc8548-pcie";









		device_type = "pci";









		pcie@0 {









			reg = <0x0 0x0 0x0 0x0 0x0>;









			#size-cells = <2>;









			#address-cells = <3>;









			device_type = "pci";









			ranges = <0x02000000 0x0 0xa0000000









				  0x02000000 0x0 0xa0000000









				  0x0 0x10000000



















				  0x01000000 0x0 0x00000000









				  0x01000000 0x0 0x00000000









				  0x0 0x00800000>;









		};









	};









};