Commit 6276a403 authored by Abel Vesa's avatar Abel Vesa Committed by Lorenzo Pieralisi
Browse files

PCI: qcom: Add SM8550 PCIe support 

SM8550 requires two additional clocks for proper working.

Add these two clocks as optional clocks (as only required by this
platform) and compatible for this platform.

While at it, let's also rename the reset variable to "rst" from
"pci_reset" to match the existing naming preference.

Link: https://lore.kernel.org/r/20230320144658.1794991-2-abel.vesa@linaro.org


Signed-off-by: default avatarAbel Vesa <abel.vesa@linaro.org>
[lpieralisi@kernel.org: commit log rewording]
Signed-off-by: default avatarLorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: default avatarManivannan Sadhasivam <mani@kernel.org>
Reviewed-by: default avatarJohan Hovold <johan+linaro@kernel.org>
parent 1a24edc3

drivers/pci/controller/dwc/pcie-qcom.c

+14 −11
Original line number Diff line number Diff line
@@ -193,13 +193,13 @@ struct qcom_pcie_resources_2_4_0 { 
	int num_resets;

};



#define QCOM_PCIE_2_7_0_MAX_CLOCKS		13

#define QCOM_PCIE_2_7_0_MAX_CLOCKS		15

#define QCOM_PCIE_2_7_0_MAX_SUPPLIES		2

struct qcom_pcie_resources_2_7_0 {

	struct clk_bulk_data clks[QCOM_PCIE_2_7_0_MAX_CLOCKS];

	int num_clks;

	struct regulator_bulk_data supplies[QCOM_PCIE_2_7_0_MAX_SUPPLIES];

	struct reset_control *pci_reset;

	struct reset_control *rst;

};



#define QCOM_PCIE_2_9_0_MAX_CLOCKS		5
@@ -848,9 +848,9 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) 
	unsigned int idx;

	int ret;



	res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");

	if (IS_ERR(res->pci_reset))

		return PTR_ERR(res->pci_reset);

	res->rst = devm_reset_control_array_get_exclusive(dev);

	if (IS_ERR(res->rst))

		return PTR_ERR(res->rst);



	res->supplies[0].supply = "vdda";

	res->supplies[1].supply = "vddpe-3v3";
@@ -876,10 +876,12 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) 
	res->clks[idx++].id = "ddrss_sf_tbu";

	res->clks[idx++].id = "aggre0";

	res->clks[idx++].id = "aggre1";

	res->clks[idx++].id = "noc_aggr";

	res->clks[idx++].id = "noc_aggr_4";

	res->clks[idx++].id = "noc_aggr_south_sf";

	res->clks[idx++].id = "cnoc_qx";

	res->clks[idx++].id = "sleep";

	res->clks[idx++].id = "cnoc_sf_axi";



	num_opt_clks = idx - num_clks;

	res->num_clks = idx;
@@ -909,17 +911,17 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) 
	if (ret < 0)

		goto err_disable_regulators;



	ret = reset_control_assert(res->pci_reset);

	if (ret < 0) {

		dev_err(dev, "cannot assert pci reset\n");

	ret = reset_control_assert(res->rst);

	if (ret) {

		dev_err(dev, "reset assert failed (%d)\n", ret);

		goto err_disable_clocks;

	}



	usleep_range(1000, 1500);



	ret = reset_control_deassert(res->pci_reset);

	if (ret < 0) {

		dev_err(dev, "cannot deassert pci reset\n");

	ret = reset_control_deassert(res->rst);

	if (ret) {

		dev_err(dev, "reset deassert failed (%d)\n", ret);

		goto err_disable_clocks;

	}
@@ -1618,6 +1620,7 @@ static const struct of_device_id qcom_pcie_match[] = { 
	{ .compatible = "qcom,pcie-sm8350", .data = &cfg_1_9_0 },

	{ .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 },

	{ .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 },

	{ .compatible = "qcom,pcie-sm8550", .data = &cfg_1_9_0 },

	{ }

};