Commit 6266992c authored by Lucas De Marchi's avatar Lucas De Marchi
Browse files

drm/i915/gt: remove GRAPHICS_VER == 10 



Replace all remaining handling of GRAPHICS_VER {==,>=} 10 with
{==,>=} 11. With the removal of CNL, there is no platform with graphics
version equals 10.

Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210728220326.1578242-5-lucas.demarchi@intel.com
parent 701d3186

drivers/gpu/drm/i915/gt/debugfs_gt_pm.c

+5 −5
Original line number Diff line number Diff line
@@ -437,20 +437,20 @@ static int frequency_show(struct seq_file *m, void *unused) 
		max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 0 :

			    rp_state_cap >> 16) & 0xff;

		max_freq *= (IS_GEN9_BC(i915) ||

			     GRAPHICS_VER(i915) >= 10 ? GEN9_FREQ_SCALER : 1);

			     GRAPHICS_VER(i915) >= 11 ? GEN9_FREQ_SCALER : 1);

		seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",

			   intel_gpu_freq(rps, max_freq));



		max_freq = (rp_state_cap & 0xff00) >> 8;

		max_freq *= (IS_GEN9_BC(i915) ||

			     GRAPHICS_VER(i915) >= 10 ? GEN9_FREQ_SCALER : 1);

			     GRAPHICS_VER(i915) >= 11 ? GEN9_FREQ_SCALER : 1);

		seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",

			   intel_gpu_freq(rps, max_freq));



		max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 16 :

			    rp_state_cap >> 0) & 0xff;

		max_freq *= (IS_GEN9_BC(i915) ||

			     GRAPHICS_VER(i915) >= 10 ? GEN9_FREQ_SCALER : 1);

			     GRAPHICS_VER(i915) >= 11 ? GEN9_FREQ_SCALER : 1);

		seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",

			   intel_gpu_freq(rps, max_freq));

		seq_printf(m, "Max overclocked frequency: %dMHz\n",
@@ -500,7 +500,7 @@ static int llc_show(struct seq_file *m, void *data) 


	min_gpu_freq = rps->min_freq;

	max_gpu_freq = rps->max_freq;

	if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 10) {

	if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 11) {

		/* Convert GT frequency to 50 HZ units */

		min_gpu_freq /= GEN9_FREQ_SCALER;

		max_gpu_freq /= GEN9_FREQ_SCALER;
@@ -518,7 +518,7 @@ static int llc_show(struct seq_file *m, void *data) 
			   intel_gpu_freq(rps,

					  (gpu_freq *

					   (IS_GEN9_BC(i915) ||

					    GRAPHICS_VER(i915) >= 10 ?

					    GRAPHICS_VER(i915) >= 11 ?

					    GEN9_FREQ_SCALER : 1))),

			   ((ia_freq >> 0) & 0xff) * 100,

			   ((ia_freq >> 8) & 0xff) * 100);

drivers/gpu/drm/i915/gt/intel_engine_cs.c

+0 −3
Original line number Diff line number Diff line
@@ -35,7 +35,6 @@ 
#define DEFAULT_LR_CONTEXT_RENDER_SIZE	(22 * PAGE_SIZE)

#define GEN8_LR_CONTEXT_RENDER_SIZE	(20 * PAGE_SIZE)

#define GEN9_LR_CONTEXT_RENDER_SIZE	(22 * PAGE_SIZE)

#define GEN10_LR_CONTEXT_RENDER_SIZE	(18 * PAGE_SIZE)

#define GEN11_LR_CONTEXT_RENDER_SIZE	(14 * PAGE_SIZE)



#define GEN8_LR_CONTEXT_OTHER_SIZE	( 2 * PAGE_SIZE)
@@ -186,8 +185,6 @@ u32 intel_engine_context_size(struct intel_gt *gt, u8 class) 
		case 12:

		case 11:

			return GEN11_LR_CONTEXT_RENDER_SIZE;

		case 10:

			return GEN10_LR_CONTEXT_RENDER_SIZE;

		case 9:

			return GEN9_LR_CONTEXT_RENDER_SIZE;

		case 8:

drivers/gpu/drm/i915/gt/intel_ggtt.c

+2 −2
Original line number Diff line number Diff line
@@ -826,13 +826,13 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size) 
	phys_addr = pci_resource_start(pdev, 0) + pci_resource_len(pdev, 0) / 2;



	/*

	 * On BXT+/CNL+ writes larger than 64 bit to the GTT pagetable range

	 * On BXT+/ICL+ writes larger than 64 bit to the GTT pagetable range

	 * will be dropped. For WC mappings in general we have 64 byte burst

	 * writes when the WC buffer is flushed, so we can't use it, but have to

	 * resort to an uncached mapping. The WC issue is easily caught by the

	 * readback check when writing GTT PTE entries.

	 */

	if (IS_GEN9_LP(i915) || GRAPHICS_VER(i915) >= 10)

	if (IS_GEN9_LP(i915) || GRAPHICS_VER(i915) >= 11)

		ggtt->gsm = ioremap(phys_addr, size);

	else

		ggtt->gsm = ioremap_wc(phys_addr, size);

drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c

+5 −5
Original line number Diff line number Diff line
@@ -24,7 +24,7 @@ static u32 read_reference_ts_freq(struct intel_uncore *uncore) 
	return base_freq + frac_freq;

}



static u32 gen10_get_crystal_clock_freq(struct intel_uncore *uncore,

static u32 gen9_get_crystal_clock_freq(struct intel_uncore *uncore,

				       u32 rpm_config_reg)

{

	u32 f19_2_mhz = 19200000;
@@ -128,10 +128,10 @@ static u32 read_clock_frequency(struct intel_uncore *uncore) 
		} else {

			u32 c0 = intel_uncore_read(uncore, RPM_CONFIG0);



			if (GRAPHICS_VER(uncore->i915) <= 10)

				freq = gen10_get_crystal_clock_freq(uncore, c0);

			else

			if (GRAPHICS_VER(uncore->i915) >= 11)

				freq = gen11_get_crystal_clock_freq(uncore, c0);

			else

				freq = gen9_get_crystal_clock_freq(uncore, c0);



			/*

			 * Now figure out how the command stream's timestamp

drivers/gpu/drm/i915/gt/intel_gtt.c

+3 −3
Original line number Diff line number Diff line
@@ -426,7 +426,7 @@ static void tgl_setup_private_ppat(struct intel_uncore *uncore) 
	intel_uncore_write(uncore, GEN12_PAT_INDEX(7), GEN8_PPAT_WB);

}



static void cnl_setup_private_ppat(struct intel_uncore *uncore)

static void icl_setup_private_ppat(struct intel_uncore *uncore)

{

	intel_uncore_write(uncore,

			   GEN10_PAT_INDEX(0),
@@ -526,8 +526,8 @@ void setup_private_pat(struct intel_uncore *uncore) 


	if (GRAPHICS_VER(i915) >= 12)

		tgl_setup_private_ppat(uncore);

	else if (GRAPHICS_VER(i915) >= 10)

		cnl_setup_private_ppat(uncore);

	else if (GRAPHICS_VER(i915) >= 11)

		icl_setup_private_ppat(uncore);

	else if (IS_CHERRYVIEW(i915) || IS_GEN9_LP(i915))

		chv_setup_private_ppat(uncore);

	else