dt-bindings: net: dsa: sja1105: convert to YAML schema

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/net/dsa/nxp,sja1105.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP SJA1105 Automotive Ethernet Switch Family Device Tree Bindings

description:

  The SJA1105 SPI interface requires a CS-to-CLK time (t2 in UM10944.pdf) of at

  least one half of t_CLK. At an SPI frequency of 1MHz, this means a minimum

  cs_sck_delay of 500ns. Ensuring that this SPI timing requirement is observed

  depends on the SPI bus master driver.

allOf:

  - $ref: "dsa.yaml#"

maintainers:

  - Vladimir Oltean <vladimir.oltean@nxp.com>

properties:

  compatible:

    enum:

      - nxp,sja1105e

      - nxp,sja1105t

      - nxp,sja1105p

      - nxp,sja1105q

      - nxp,sja1105r

      - nxp,sja1105s

  reg:

    maxItems: 1

required:

  - compatible

  - reg

unevaluatedProperties: false

examples:

  - |

    spi {

            #address-cells = <1>;

            #size-cells = <0>;

            ethernet-switch@1 {

                    reg = <0x1>;

                    compatible = "nxp,sja1105t";

                    ethernet-ports {

                            #address-cells = <1>;

                            #size-cells = <0>;

                            port@0 {

                                    phy-handle = <&rgmii_phy6>;

                                    phy-mode = "rgmii-id";

                                    reg = <0>;

                            };

                            port@1 {

                                    phy-handle = <&rgmii_phy3>;

                                    phy-mode = "rgmii-id";

                                    reg = <1>;

                            };

                            port@2 {

                                    phy-handle = <&rgmii_phy4>;

                                    phy-mode = "rgmii-id";

                                    reg = <2>;

                            };

                            port@3 {

                                    phy-mode = "rgmii-id";

                                    reg = <3>;

                            };

                            port@4 {

                                    ethernet = <&enet2>;

                                    phy-mode = "rgmii";

                                    reg = <4>;

                                    fixed-link {

                                            speed = <1000>;

                                            full-duplex;

                                    };

                            };

                    };

            };

    };

NXP SJA1105 switch driver

=========================

Required properties:

- compatible:

	Must be one of:

	- "nxp,sja1105e"

	- "nxp,sja1105t"

	- "nxp,sja1105p"

	- "nxp,sja1105q"

	- "nxp,sja1105r"

	- "nxp,sja1105s"

	Although the device ID could be detected at runtime, explicit bindings

	are required in order to be able to statically check their validity.

	For example, SGMII can only be specified on port 4 of R and S devices,

	and the non-SGMII devices, while pin-compatible, are not equal in terms

	of support for RGMII internal delays (supported on P/Q/R/S, but not on

	E/T).

See Documentation/devicetree/bindings/net/dsa/dsa.txt for the list of standard

DSA required and optional properties.

Other observations

------------------

The SJA1105 SPI interface requires a CS-to-CLK time (t2 in UM10944) of at least

one half of t_CLK. At an SPI frequency of 1MHz, this means a minimum

cs_sck_delay of 500ns. Ensuring that this SPI timing requirement is observed

depends on the SPI bus master driver.

Example

-------

Ethernet switch connected via SPI to the host, CPU port wired to enet2:

arch/arm/boot/dts/ls1021a-tsn.dts:

/* SPI controller of the LS1021 */

&dspi0 {

	sja1105@1 {

		reg = <0x1>;

		#address-cells = <1>;

		#size-cells = <0>;

		compatible = "nxp,sja1105t";

		spi-max-frequency = <4000000>;

		fsl,spi-cs-sck-delay = <1000>;

		fsl,spi-sck-cs-delay = <1000>;

		ports {

			#address-cells = <1>;

			#size-cells = <0>;

			port@0 {

				/* ETH5 written on chassis */

				label = "swp5";

				phy-handle = <&rgmii_phy6>;

				phy-mode = "rgmii-id";

				reg = <0>;

			};

			port@1 {

				/* ETH2 written on chassis */

				label = "swp2";

				phy-handle = <&rgmii_phy3>;

				phy-mode = "rgmii-id";

				reg = <1>;

			};

			port@2 {

				/* ETH3 written on chassis */

				label = "swp3";

				phy-handle = <&rgmii_phy4>;

				phy-mode = "rgmii-id";

				reg = <2>;

			};

			port@3 {

				/* ETH4 written on chassis */

				phy-handle = <&rgmii_phy5>;

				label = "swp4";

				phy-mode = "rgmii-id";

				reg = <3>;

			};

			port@4 {

				/* Internal port connected to eth2 */

				ethernet = <&enet2>;

				phy-mode = "rgmii";

				reg = <4>;

				fixed-link {

					speed = <1000>;

					full-duplex;

				};

			};

		};

	};

};

/* MDIO controller of the LS1021 */

&mdio0 {

	/* BCM5464 */

	rgmii_phy3: ethernet-phy@3 {

		reg = <0x3>;

	};

	rgmii_phy4: ethernet-phy@4 {

		reg = <0x4>;

	};

	rgmii_phy5: ethernet-phy@5 {

		reg = <0x5>;

	};

	rgmii_phy6: ethernet-phy@6 {

		reg = <0x6>;

	};

};

/* Ethernet master port of the LS1021 */

&enet2 {

	phy-connection-type = "rgmii";

	status = "ok";

	fixed-link {

		speed = <1000>;

		full-duplex;

	};

};