Commit 6246059a authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu: simplify amdgpu_ras_eeprom.c 



All chips that support RAS also support IP discovery, so
use the IP versions rather than a mix of IP versions and
asic types.  Checking the validity of the atom_ctx pointer
is not required as the vbios is already fetched at this
point.

v2: add comments to id asic types based on feedback from Luben

Reviewed-by: default avatarLuben Tuikov <luben.tuikov@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc: Luben Tuikov <luben.tuikov@amd.com>
parent 27488686

drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c

+20 −52
Original line number Diff line number Diff line
@@ -107,9 +107,11 @@ 


static bool __is_ras_eeprom_supported(struct amdgpu_device *adev)

{

	if (adev->asic_type == CHIP_IP_DISCOVERY) {

	switch (adev->ip_versions[MP1_HWIP][0]) {

	case IP_VERSION(11, 0, 2): /* VEGA20 and ARCTURUS */

	case IP_VERSION(11, 0, 7): /* Sienna cichlid */

	case IP_VERSION(13, 0, 0):

	case IP_VERSION(13, 0, 2): /* Aldebaran */

	case IP_VERSION(13, 0, 10):

		return true;

	default:
@@ -117,43 +119,6 @@ static bool __is_ras_eeprom_supported(struct amdgpu_device *adev) 
	}

}



	return  adev->asic_type == CHIP_VEGA20 ||

		adev->asic_type == CHIP_ARCTURUS ||

		adev->asic_type == CHIP_SIENNA_CICHLID ||

		adev->asic_type == CHIP_ALDEBARAN;

}



static bool __get_eeprom_i2c_addr_arct(struct amdgpu_device *adev,

				       struct amdgpu_ras_eeprom_control *control)

{

	struct atom_context *atom_ctx = adev->mode_info.atom_context;



	if (!control || !atom_ctx)

		return false;



	if (strnstr(atom_ctx->vbios_version,

	            "D342",

		    sizeof(atom_ctx->vbios_version)))

		control->i2c_address = EEPROM_I2C_MADDR_0;

	else

		control->i2c_address = EEPROM_I2C_MADDR_4;



	return true;

}



static bool __get_eeprom_i2c_addr_ip_discovery(struct amdgpu_device *adev,

				       struct amdgpu_ras_eeprom_control *control)

{

	switch (adev->ip_versions[MP1_HWIP][0]) {

	case IP_VERSION(13, 0, 0):

	case IP_VERSION(13, 0, 10):

		control->i2c_address = EEPROM_I2C_MADDR_4;

		return true;

	default:

		return false;

	}

}



static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev,

				  struct amdgpu_ras_eeprom_control *control)

{
@@ -178,29 +143,32 @@ static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev, 
		return true;

	}



	switch (adev->asic_type) {

	case CHIP_VEGA20:

	switch (adev->ip_versions[MP1_HWIP][0]) {

	case IP_VERSION(11, 0, 2):

		/* VEGA20 and ARCTURUS */

		if (adev->asic_type == CHIP_VEGA20)

			control->i2c_address = EEPROM_I2C_MADDR_0;

		else if (strnstr(atom_ctx->vbios_version,

				 "D342",

				 sizeof(atom_ctx->vbios_version)))

			control->i2c_address = EEPROM_I2C_MADDR_0;

		else

			control->i2c_address = EEPROM_I2C_MADDR_4;

		return true;



	case CHIP_ARCTURUS:

		return __get_eeprom_i2c_addr_arct(adev, control);



	case CHIP_SIENNA_CICHLID:

	case IP_VERSION(11, 0, 7):

		control->i2c_address = EEPROM_I2C_MADDR_0;

		return true;



	case CHIP_ALDEBARAN:

	case IP_VERSION(13, 0, 2):

		if (strnstr(atom_ctx->vbios_version, "D673",

			    sizeof(atom_ctx->vbios_version)))

			control->i2c_address = EEPROM_I2C_MADDR_4;

		else

			control->i2c_address = EEPROM_I2C_MADDR_0;

		return true;



	case CHIP_IP_DISCOVERY:

		return __get_eeprom_i2c_addr_ip_discovery(adev, control);



	case IP_VERSION(13, 0, 0):

	case IP_VERSION(13, 0, 10):

		control->i2c_address = EEPROM_I2C_MADDR_4;

		return true;

	default:

		return false;

	}