Commit 621427fb authored by Tommaso Merciai's avatar Tommaso Merciai Committed by David S. Miller
Browse files

net: phy: DP83822: enable rgmii mode if phy_interface_is_rgmii 

RGMII mode can be enable from dp83822 straps, and also writing bit 9
of register 0x17 - RMII and Status Register (RCSR).
When phy_interface_is_rgmii rgmii mode must be enabled, same for
contrary, this prevents malconfigurations of hw straps

References:
 - https://www.ti.com/lit/gpn/dp83822i

 p66

Signed-off-by: default avatarTommaso Merciai <tommaso.merciai@amarulasolutions.com>
Co-developed-by: default avatarMichael Trimarchi <michael@amarulasolutions.com>
Suggested-by: default avatarAlberto Bianchi <alberto.bianchi@amarulasolutions.com>
Tested-by: default avatarTommaso Merciai <tommaso.merciai@amarulasolutions.com>
Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent a3f7404c

drivers/net/phy/dp83822.c

+8 −1
Original line number Diff line number Diff line
@@ -94,7 +94,8 @@ 
#define DP83822_WOL_INDICATION_SEL BIT(8)

#define DP83822_WOL_CLR_INDICATION BIT(11)



/* RSCR bits */

/* RCSR bits */

#define DP83822_RGMII_MODE_EN	BIT(9)

#define DP83822_RX_CLK_SHIFT	BIT(12)

#define DP83822_TX_CLK_SHIFT	BIT(11)
@@ -408,6 +409,12 @@ static int dp83822_config_init(struct phy_device *phydev) 
			if (err)

				return err;

		}



		phy_set_bits_mmd(phydev, DP83822_DEVADDR,

					MII_DP83822_RCSR, DP83822_RGMII_MODE_EN);

	} else {

		phy_clear_bits_mmd(phydev, DP83822_DEVADDR,

					MII_DP83822_RCSR, DP83822_RGMII_MODE_EN);

	}



	if (dp83822->fx_enabled) {