Commit 61c5ed94 authored by Michael Cheng's avatar Michael Cheng Committed by Matt Roper
Browse files

drm/i915/gt: replace cache_clflush_range 



Replace all occurrence of cache_clflush_range with drm_clflush_virt_range.
This will prevent compile errors on non-x86 platforms.

Signed-off-by: default avatarMichael Cheng <michael.cheng@intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220321223819.72833-6-michael.cheng@intel.com
parent 89754df8

drivers/gpu/drm/i915/gt/gen8_ppgtt.c

+6 −6
Original line number Diff line number Diff line
@@ -454,11 +454,11 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt, 
				pd = pdp->entry[gen8_pd_index(idx, 2)];

			}



			clflush_cache_range(vaddr, PAGE_SIZE);

			drm_clflush_virt_range(vaddr, PAGE_SIZE);

			vaddr = px_vaddr(i915_pt_entry(pd, gen8_pd_index(idx, 1)));

		}

	} while (1);

	clflush_cache_range(vaddr, PAGE_SIZE);

	drm_clflush_virt_range(vaddr, PAGE_SIZE);



	return idx;

}
@@ -631,7 +631,7 @@ static void gen8_ppgtt_insert_huge(struct i915_address_space *vm, 
			}

		} while (rem >= page_size && index < I915_PDES);



		clflush_cache_range(vaddr, PAGE_SIZE);

		drm_clflush_virt_range(vaddr, PAGE_SIZE);



		/*

		 * Is it safe to mark the 2M block as 64K? -- Either we have
@@ -647,7 +647,7 @@ static void gen8_ppgtt_insert_huge(struct i915_address_space *vm, 
					      I915_GTT_PAGE_SIZE_2M)))) {

			vaddr = px_vaddr(pd);

			vaddr[maybe_64K] |= GEN8_PDE_IPS_64K;

			clflush_cache_range(vaddr, PAGE_SIZE);

			drm_clflush_virt_range(vaddr, PAGE_SIZE);

			page_size = I915_GTT_PAGE_SIZE_64K;



			/*
@@ -668,7 +668,7 @@ static void gen8_ppgtt_insert_huge(struct i915_address_space *vm, 
				for (i = 1; i < index; i += 16)

					memset64(vaddr + i, encode, 15);



				clflush_cache_range(vaddr, PAGE_SIZE);

				drm_clflush_virt_range(vaddr, PAGE_SIZE);

			}

		}
@@ -722,7 +722,7 @@ static void gen8_ppgtt_insert_entry(struct i915_address_space *vm, 


	vaddr = px_vaddr(pt);

	vaddr[gen8_pd_index(idx, 0)] = gen8_pte_encode(addr, level, flags);

	clflush_cache_range(&vaddr[gen8_pd_index(idx, 0)], sizeof(*vaddr));

	drm_clflush_virt_range(&vaddr[gen8_pd_index(idx, 0)], sizeof(*vaddr));

}



static void __xehpsdv_ppgtt_insert_entry_lm(struct i915_address_space *vm,

drivers/gpu/drm/i915/gt/intel_execlists_submission.c

+1 −1
Original line number Diff line number Diff line
@@ -2827,7 +2827,7 @@ static void execlists_sanitize(struct intel_engine_cs *engine) 
	sanitize_hwsp(engine);



	/* And scrub the dirty cachelines for the HWSP */

	clflush_cache_range(engine->status_page.addr, PAGE_SIZE);

	drm_clflush_virt_range(engine->status_page.addr, PAGE_SIZE);



	intel_engine_reset_pinned_contexts(engine);

}

drivers/gpu/drm/i915/gt/intel_gtt.c

+1 −1
Original line number Diff line number Diff line
@@ -298,7 +298,7 @@ fill_page_dma(struct drm_i915_gem_object *p, const u64 val, unsigned int count) 
	void *vaddr = __px_vaddr(p);



	memset64(vaddr, val, count);

	clflush_cache_range(vaddr, PAGE_SIZE);

	drm_clflush_virt_range(vaddr, PAGE_SIZE);

}



static void poison_scratch_page(struct drm_i915_gem_object *scratch)

drivers/gpu/drm/i915/gt/intel_ppgtt.c

+1 −1
Original line number Diff line number Diff line
@@ -91,7 +91,7 @@ write_dma_entry(struct drm_i915_gem_object * const pdma, 
	u64 * const vaddr = __px_vaddr(pdma);



	vaddr[idx] = encoded_entry;

	clflush_cache_range(&vaddr[idx], sizeof(u64));

	drm_clflush_virt_range(&vaddr[idx], sizeof(u64));

}



void

drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c

+1 −1
Original line number Diff line number Diff line
@@ -3581,7 +3581,7 @@ static void guc_sanitize(struct intel_engine_cs *engine) 
	sanitize_hwsp(engine);



	/* And scrub the dirty cachelines for the HWSP */

	clflush_cache_range(engine->status_page.addr, PAGE_SIZE);

	drm_clflush_virt_range(engine->status_page.addr, PAGE_SIZE);



	intel_engine_reset_pinned_contexts(engine);

}