Commit 61a7c96b authored by Sandipan Das's avatar Sandipan Das Committed by PvsNarasimha
Browse files

perf/x86/amd/core: Define a proper ref-cycles event for Zen 4 and later

mainline inclusion
from mainline-v6.9-rc2
commit 68cdf1e6e8f2ce78ed7d8f5d80844fd75a9c54ff
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/IAU6ZD

Reference: https://github.com/torvalds/linux/commit/68cdf1e6e8f2ce78ed7d8f5d80844fd75a9c54ff



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commit 68cdf1e6e8f2ce78ed7d8f5d80844fd75a9c54ff upstream

Add the "ref-cycles" event for AMD processors based on Zen 4 and later
microarchitectures. The backing event is based on PMCx120 which counts
cycles not in halt state in P0 frequency (same as MPERF).

Signed-off-by: default avatarSandipan Das <sandipan.das@amd.com>
Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
Reviewed-by: default avatarIan Rogers <irogers@google.com>
Link: https://lore.kernel.org/r/089155f19f7c7e65aeb1caa727a882e2ca9b8b04.1711352180.git.sandipan.das@amd.com


Signed-off-by: default avatarPvsNarasimha <PVS.NarasimhaRao@amd.com>
parent f7097fd5
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+15 −0
Original line number Diff line number Diff line
@@ -274,8 +274,23 @@ static const u64 amd_zen2_perfmon_event_map[PERF_COUNT_HW_MAX] =
	[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND]	= 0x00a9,
};

static const u64 amd_zen4_perfmon_event_map[PERF_COUNT_HW_MAX] =
{
	[PERF_COUNT_HW_CPU_CYCLES]		= 0x0076,
	[PERF_COUNT_HW_INSTRUCTIONS]		= 0x00c0,
	[PERF_COUNT_HW_CACHE_REFERENCES]	= 0xff60,
	[PERF_COUNT_HW_CACHE_MISSES]		= 0x0964,
	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS]	= 0x00c2,
	[PERF_COUNT_HW_BRANCH_MISSES]		= 0x00c3,
	[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND]	= 0x00a9,
	[PERF_COUNT_HW_REF_CPU_CYCLES]		= 0x100000120,
};

static u64 amd_pmu_event_map(int hw_event)
{
	if (cpu_feature_enabled(X86_FEATURE_ZEN4) || boot_cpu_data.x86 >= 0x1a)
		return amd_zen4_perfmon_event_map[hw_event];

	if (cpu_feature_enabled(X86_FEATURE_ZEN2) || boot_cpu_data.x86 >= 0x19)
		return amd_zen2_perfmon_event_map[hw_event];