Commit 618ff55e authored by Will Deacon's avatar Will Deacon
Browse files

Merge branch 'for-next/sysregs' into for-next/core 

* for-next/sysregs: (28 commits)
  arm64/sysreg: Convert ID_AA64ZFR0_EL1 to automatic generation
  arm64/sysreg: Convert ID_AA64SMFR0_EL1 to automatic generation
  arm64/sysreg: Convert LORID_EL1 to automatic generation
  arm64/sysreg: Convert LORC_EL1 to automatic generation
  arm64/sysreg: Convert LORN_EL1 to automatic generation
  arm64/sysreg: Convert LOREA_EL1 to automatic generation
  arm64/sysreg: Convert LORSA_EL1 to automatic generation
  arm64/sysreg: Convert ID_AA64ISAR2_EL1 to automatic generation
  arm64/sysreg: Convert ID_AA64ISAR1_EL1 to automatic generation
  arm64/sysreg: Convert GMID to automatic generation
  arm64/sysreg: Convert DCZID_EL0 to automatic generation
  arm64/sysreg: Convert CTR_EL0 to automatic generation
  arm64/sysreg: Add _EL1 into ID_AA64ISAR2_EL1 definition names
  arm64/sysreg: Add _EL1 into ID_AA64ISAR1_EL1 definition names
  arm64/sysreg: Remove defines for RPRES enumeration
  arm64/sysreg: Standardise naming for ID_AA64ZFR0_EL1 fields
  arm64/sysreg: Standardise naming for ID_AA64SMFR0_EL1 enums
  arm64/sysreg: Standardise naming for WFxT defines
  arm64/sysreg: Make BHB clear feature defines match the architecture
  arm64/sysreg: Align pointer auth enumeration defines with architecture
  ...
parents cb20311e 3bbeca99

arch/arm64/include/asm/asm_pointer_auth.h

+2 −2
Original line number Diff line number Diff line
@@ -59,9 +59,9 @@ alternative_else_nop_endif 


	.macro __ptrauth_keys_init_cpu tsk, tmp1, tmp2, tmp3

	mrs	\tmp1, id_aa64isar1_el1

	ubfx	\tmp1, \tmp1, #ID_AA64ISAR1_APA_SHIFT, #8

	ubfx	\tmp1, \tmp1, #ID_AA64ISAR1_EL1_APA_SHIFT, #8

	mrs_s	\tmp2, SYS_ID_AA64ISAR2_EL1

	ubfx	\tmp2, \tmp2, #ID_AA64ISAR2_APA3_SHIFT, #4

	ubfx	\tmp2, \tmp2, #ID_AA64ISAR2_EL1_APA3_SHIFT, #4

	orr	\tmp1, \tmp1, \tmp2

	cbz	\tmp1, .Lno_addr_auth\@

	mov_q	\tmp1, (SCTLR_ELx_ENIA | SCTLR_ELx_ENIB | \

arch/arm64/include/asm/cache.h

+13 −28
Original line number Diff line number Diff line
@@ -5,34 +5,9 @@ 
#ifndef __ASM_CACHE_H

#define __ASM_CACHE_H



#include <asm/cputype.h>

#include <asm/mte-def.h>



#define CTR_L1IP_SHIFT		14

#define CTR_L1IP_MASK		3

#define CTR_DMINLINE_SHIFT	16

#define CTR_IMINLINE_SHIFT	0

#define CTR_IMINLINE_MASK	0xf

#define CTR_ERG_SHIFT		20

#define CTR_CWG_SHIFT		24

#define CTR_CWG_MASK		15

#define CTR_IDC_SHIFT		28

#define CTR_DIC_SHIFT		29



#define CTR_CACHE_MINLINE_MASK	\

	(0xf << CTR_DMINLINE_SHIFT | CTR_IMINLINE_MASK << CTR_IMINLINE_SHIFT)



#define CTR_L1IP(ctr)		(((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK)



#define ICACHE_POLICY_VPIPT	0

#define ICACHE_POLICY_RESERVED	1

#define ICACHE_POLICY_VIPT	2

#define ICACHE_POLICY_PIPT	3



#define L1_CACHE_SHIFT		(6)

#define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)





#define CLIDR_LOUU_SHIFT	27

#define CLIDR_LOC_SHIFT		24

#define CLIDR_LOUIS_SHIFT	21
@@ -55,6 +30,10 @@ 
#include <linux/bitops.h>

#include <linux/kasan-enabled.h>



#include <asm/cputype.h>

#include <asm/mte-def.h>

#include <asm/sysreg.h>



#ifdef CONFIG_KASAN_SW_TAGS

#define ARCH_SLAB_MINALIGN	(1ULL << KASAN_SHADOW_SCALE_SHIFT)

#elif defined(CONFIG_KASAN_HW_TAGS)
@@ -66,6 +45,12 @@ static inline unsigned int arch_slab_minalign(void) 
#define arch_slab_minalign() arch_slab_minalign()

#endif



#define CTR_CACHE_MINLINE_MASK	\

	(0xf << CTR_EL0_DMINLINE_SHIFT | \

	 CTR_EL0_IMINLINE_MASK << CTR_EL0_IMINLINE_SHIFT)



#define CTR_L1IP(ctr)		SYS_FIELD_GET(CTR_EL0, L1Ip, ctr)



#define ICACHEF_ALIASING	0

#define ICACHEF_VPIPT		1

extern unsigned long __icache_flags;
@@ -86,7 +71,7 @@ static __always_inline int icache_is_vpipt(void) 


static inline u32 cache_type_cwg(void)

{

	return (read_cpuid_cachetype() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;

	return (read_cpuid_cachetype() >> CTR_EL0_CWG_SHIFT) & CTR_EL0_CWG_MASK;

}



#define __read_mostly __section(".data..read_mostly")
@@ -120,12 +105,12 @@ static inline u32 __attribute_const__ read_cpuid_effective_cachetype(void) 
{

	u32 ctr = read_cpuid_cachetype();



	if (!(ctr & BIT(CTR_IDC_SHIFT))) {

	if (!(ctr & BIT(CTR_EL0_IDC_SHIFT))) {

		u64 clidr = read_sysreg(clidr_el1);



		if (CLIDR_LOC(clidr) == 0 ||

		    (CLIDR_LOUIS(clidr) == 0 && CLIDR_LOUU(clidr) == 0))

			ctr |= BIT(CTR_IDC_SHIFT);

			ctr |= BIT(CTR_EL0_IDC_SHIFT);

	}



	return ctr;

arch/arm64/include/asm/cpufeature.h

+1 −1
Original line number Diff line number Diff line
@@ -673,7 +673,7 @@ static inline bool supports_clearbhb(int scope) 
		isar2 = read_sanitised_ftr_reg(SYS_ID_AA64ISAR2_EL1);



	return cpuid_feature_extract_unsigned_field(isar2,

						    ID_AA64ISAR2_CLEARBHB_SHIFT);

						    ID_AA64ISAR2_EL1_BC_SHIFT);

}



const struct cpumask *system_32bit_el0_cpumask(void);

arch/arm64/include/asm/el2_setup.h

+1 −1
Original line number Diff line number Diff line
@@ -161,7 +161,7 @@ 
	mov	x1, #0				// SMCR controls



	mrs_s	x2, SYS_ID_AA64SMFR0_EL1

	ubfx	x2, x2, #ID_AA64SMFR0_FA64_SHIFT, #1 // Full FP in SM?

	ubfx	x2, x2, #ID_AA64SMFR0_EL1_FA64_SHIFT, #1 // Full FP in SM?

	cbz	x2, .Lskip_sme_fa64_\@



	orr	x1, x1, SMCR_ELx_FA64_MASK

arch/arm64/include/asm/sysreg.h

+5 −119
Original line number Diff line number Diff line
@@ -192,8 +192,6 @@ 


#define SYS_ID_AA64PFR0_EL1		sys_reg(3, 0, 0, 4, 0)

#define SYS_ID_AA64PFR1_EL1		sys_reg(3, 0, 0, 4, 1)

#define SYS_ID_AA64ZFR0_EL1		sys_reg(3, 0, 0, 4, 4)

#define SYS_ID_AA64SMFR0_EL1		sys_reg(3, 0, 0, 4, 5)



#define SYS_ID_AA64DFR0_EL1		sys_reg(3, 0, 0, 5, 0)

#define SYS_ID_AA64DFR1_EL1		sys_reg(3, 0, 0, 5, 1)
@@ -201,9 +199,6 @@ 
#define SYS_ID_AA64AFR0_EL1		sys_reg(3, 0, 0, 5, 4)

#define SYS_ID_AA64AFR1_EL1		sys_reg(3, 0, 0, 5, 5)



#define SYS_ID_AA64ISAR1_EL1		sys_reg(3, 0, 0, 6, 1)

#define SYS_ID_AA64ISAR2_EL1		sys_reg(3, 0, 0, 6, 2)



#define SYS_ID_AA64MMFR0_EL1		sys_reg(3, 0, 0, 7, 0)

#define SYS_ID_AA64MMFR1_EL1		sys_reg(3, 0, 0, 7, 1)

#define SYS_ID_AA64MMFR2_EL1		sys_reg(3, 0, 0, 7, 2)
@@ -410,12 +405,6 @@ 
#define SYS_MAIR_EL1			sys_reg(3, 0, 10, 2, 0)

#define SYS_AMAIR_EL1			sys_reg(3, 0, 10, 3, 0)



#define SYS_LORSA_EL1			sys_reg(3, 0, 10, 4, 0)

#define SYS_LOREA_EL1			sys_reg(3, 0, 10, 4, 1)

#define SYS_LORN_EL1			sys_reg(3, 0, 10, 4, 2)

#define SYS_LORC_EL1			sys_reg(3, 0, 10, 4, 3)

#define SYS_LORID_EL1			sys_reg(3, 0, 10, 4, 7)



#define SYS_VBAR_EL1			sys_reg(3, 0, 12, 0, 0)

#define SYS_DISR_EL1			sys_reg(3, 0, 12, 1, 1)
@@ -454,16 +443,12 @@ 
#define SYS_CNTKCTL_EL1			sys_reg(3, 0, 14, 1, 0)



#define SYS_CCSIDR_EL1			sys_reg(3, 1, 0, 0, 0)

#define SYS_GMID_EL1			sys_reg(3, 1, 0, 0, 4)

#define SYS_AIDR_EL1			sys_reg(3, 1, 0, 0, 7)



#define SMIDR_EL1_IMPLEMENTER_SHIFT	24

#define SMIDR_EL1_SMPS_SHIFT	15

#define SMIDR_EL1_AFFINITY_SHIFT	0



#define SYS_CTR_EL0			sys_reg(3, 3, 0, 0, 1)

#define SYS_DCZID_EL0			sys_reg(3, 3, 0, 0, 7)



#define SYS_RNDR_EL0			sys_reg(3, 3, 2, 4, 0)

#define SYS_RNDRRS_EL0			sys_reg(3, 3, 2, 4, 1)
@@ -704,66 +689,6 @@ 
/* Position the attr at the correct index */

#define MAIR_ATTRIDX(attr, idx)		((attr) << ((idx) * 8))



/* id_aa64isar1 */

#define ID_AA64ISAR1_I8MM_SHIFT		52

#define ID_AA64ISAR1_DGH_SHIFT		48

#define ID_AA64ISAR1_BF16_SHIFT		44

#define ID_AA64ISAR1_SPECRES_SHIFT	40

#define ID_AA64ISAR1_SB_SHIFT		36

#define ID_AA64ISAR1_FRINTTS_SHIFT	32

#define ID_AA64ISAR1_GPI_SHIFT		28

#define ID_AA64ISAR1_GPA_SHIFT		24

#define ID_AA64ISAR1_LRCPC_SHIFT	20

#define ID_AA64ISAR1_FCMA_SHIFT		16

#define ID_AA64ISAR1_JSCVT_SHIFT	12

#define ID_AA64ISAR1_API_SHIFT		8

#define ID_AA64ISAR1_APA_SHIFT		4

#define ID_AA64ISAR1_DPB_SHIFT		0



#define ID_AA64ISAR1_APA_NI			0x0

#define ID_AA64ISAR1_APA_ARCHITECTED		0x1

#define ID_AA64ISAR1_APA_ARCH_EPAC		0x2

#define ID_AA64ISAR1_APA_ARCH_EPAC2		0x3

#define ID_AA64ISAR1_APA_ARCH_EPAC2_FPAC	0x4

#define ID_AA64ISAR1_APA_ARCH_EPAC2_FPAC_CMB	0x5

#define ID_AA64ISAR1_API_NI			0x0

#define ID_AA64ISAR1_API_IMP_DEF		0x1

#define ID_AA64ISAR1_API_IMP_DEF_EPAC		0x2

#define ID_AA64ISAR1_API_IMP_DEF_EPAC2		0x3

#define ID_AA64ISAR1_API_IMP_DEF_EPAC2_FPAC	0x4

#define ID_AA64ISAR1_API_IMP_DEF_EPAC2_FPAC_CMB	0x5

#define ID_AA64ISAR1_GPA_NI			0x0

#define ID_AA64ISAR1_GPA_ARCHITECTED		0x1

#define ID_AA64ISAR1_GPI_NI			0x0

#define ID_AA64ISAR1_GPI_IMP_DEF		0x1



/* id_aa64isar2 */

#define ID_AA64ISAR2_CLEARBHB_SHIFT	28

#define ID_AA64ISAR2_APA3_SHIFT		12

#define ID_AA64ISAR2_GPA3_SHIFT		8

#define ID_AA64ISAR2_RPRES_SHIFT	4

#define ID_AA64ISAR2_WFXT_SHIFT		0



#define ID_AA64ISAR2_RPRES_8BIT		0x0

#define ID_AA64ISAR2_RPRES_12BIT	0x1

/*

 * Value 0x1 has been removed from the architecture, and is

 * reserved, but has not yet been removed from the ARM ARM

 * as of ARM DDI 0487G.b.

 */

#define ID_AA64ISAR2_WFXT_NI		0x0

#define ID_AA64ISAR2_WFXT_SUPPORTED	0x2



#define ID_AA64ISAR2_APA3_NI			0x0

#define ID_AA64ISAR2_APA3_ARCHITECTED		0x1

#define ID_AA64ISAR2_APA3_ARCH_EPAC		0x2

#define ID_AA64ISAR2_APA3_ARCH_EPAC2		0x3

#define ID_AA64ISAR2_APA3_ARCH_EPAC2_FPAC	0x4

#define ID_AA64ISAR2_APA3_ARCH_EPAC2_FPAC_CMB	0x5



#define ID_AA64ISAR2_GPA3_NI			0x0

#define ID_AA64ISAR2_GPA3_ARCHITECTED		0x1



/* id_aa64pfr0 */

#define ID_AA64PFR0_CSV3_SHIFT		60

#define ID_AA64PFR0_CSV2_SHIFT		56
@@ -811,45 +736,6 @@ 
#define ID_AA64PFR1_MTE			0x2

#define ID_AA64PFR1_MTE_ASYMM		0x3



/* id_aa64zfr0 */

#define ID_AA64ZFR0_F64MM_SHIFT		56

#define ID_AA64ZFR0_F32MM_SHIFT		52

#define ID_AA64ZFR0_I8MM_SHIFT		44

#define ID_AA64ZFR0_SM4_SHIFT		40

#define ID_AA64ZFR0_SHA3_SHIFT		32

#define ID_AA64ZFR0_BF16_SHIFT		20

#define ID_AA64ZFR0_BITPERM_SHIFT	16

#define ID_AA64ZFR0_AES_SHIFT		4

#define ID_AA64ZFR0_SVEVER_SHIFT	0



#define ID_AA64ZFR0_F64MM		0x1

#define ID_AA64ZFR0_F32MM		0x1

#define ID_AA64ZFR0_I8MM		0x1

#define ID_AA64ZFR0_BF16		0x1

#define ID_AA64ZFR0_SM4			0x1

#define ID_AA64ZFR0_SHA3		0x1

#define ID_AA64ZFR0_BITPERM		0x1

#define ID_AA64ZFR0_AES			0x1

#define ID_AA64ZFR0_AES_PMULL		0x2

#define ID_AA64ZFR0_SVEVER_SVE2		0x1



/* id_aa64smfr0 */

#define ID_AA64SMFR0_FA64_SHIFT		63

#define ID_AA64SMFR0_I16I64_SHIFT	52

#define ID_AA64SMFR0_F64F64_SHIFT	48

#define ID_AA64SMFR0_I8I32_SHIFT	36

#define ID_AA64SMFR0_F16F32_SHIFT	35

#define ID_AA64SMFR0_B16F32_SHIFT	34

#define ID_AA64SMFR0_F32F32_SHIFT	32



#define ID_AA64SMFR0_FA64		0x1

#define ID_AA64SMFR0_I16I64		0xf

#define ID_AA64SMFR0_F64F64		0x1

#define ID_AA64SMFR0_I8I32		0xf

#define ID_AA64SMFR0_F16F32		0x1

#define ID_AA64SMFR0_B16F32		0x1

#define ID_AA64SMFR0_F32F32		0x1



/* id_aa64mmfr0 */

#define ID_AA64MMFR0_ECV_SHIFT		60

#define ID_AA64MMFR0_FGT_SHIFT		56
@@ -1084,9 +970,6 @@ 
#define MVFR2_FPMISC_SHIFT		4

#define MVFR2_SIMDMISC_SHIFT		0



#define DCZID_DZP_SHIFT			4

#define DCZID_BS_SHIFT			0



#define CPACR_EL1_FPEN_EL1EN	(BIT(20)) /* enable EL1 access */

#define CPACR_EL1_FPEN_EL0EN	(BIT(21)) /* enable EL0 access, if EL1EN set */
@@ -1121,8 +1004,8 @@ 
#define SYS_RGSR_EL1_SEED_MASK	0xffffUL



/* GMID_EL1 field definitions */

#define SYS_GMID_EL1_BS_SHIFT	0

#define SYS_GMID_EL1_BS_SIZE	4

#define GMID_EL1_BS_SHIFT	0

#define GMID_EL1_BS_SIZE	4



/* TFSR{,E0}_EL1 bit definitions */

#define SYS_TFSR_EL1_TF0_SHIFT	0
@@ -1324,6 +1207,9 @@ 


#endif



#define SYS_FIELD_GET(reg, field, val)		\

		 FIELD_GET(reg##_##field##_MASK, val)



#define SYS_FIELD_PREP(reg, field, val)		\

		 FIELD_PREP(reg##_##field##_MASK, val)