Commit 6132a490 authored by Thomas Gleixner's avatar Thomas Gleixner
Browse files

Merge tag 'irqchip-6.2' of... 

Merge tag 'irqchip-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core

Pull irqchip updates frim Marc Zyngier:

 - More APCI fixes and improvements for the LoongArch architecture,
   adding support for the HTVEC irqchip, suspend-resume, and some
   PCI INTx workarounds

 - Initial DT support for LoongArch. I'm not even kidding.

 - Support for the MTK CIRQv2, a minor deviation from the original version

 - Error handling fixes for wpcm450, GIC...

 - BE detection for a FSL controller

 - Declare the Sifive PLIC as wake-up agnostic

 - Simplify fishing out the device data for the ST irqchip

 - Mark some data structures as __initconst in the apple-aic driver

 - Switch over from strtobool to kstrtobool

 - COMPILE_TEST fixes
parents e6d22108 6ed54e17

Documentation/devicetree/bindings/interrupt-controller/loongarch,cpu-interrupt-controller.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/interrupt-controller/loongarch,cpu-interrupt-controller.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: LoongArch CPU Interrupt Controller



maintainers:

  - Liu Peibao <liupeibao@loongson.cn>



properties:

  compatible:

    const: loongarch,cpu-interrupt-controller



  '#interrupt-cells':

    const: 1



  interrupt-controller: true



additionalProperties: false



required:

  - compatible

  - '#interrupt-cells'

  - interrupt-controller



examples:

  - |

    interrupt-controller {

      compatible = "loongarch,cpu-interrupt-controller";

      #interrupt-cells = <1>;

      interrupt-controller;

    };

Documentation/devicetree/bindings/interrupt-controller/mediatek,cirq.txt

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* Mediatek 27xx cirq



In Mediatek SOCs, the CIRQ is a low power interrupt controller designed to

work outside MCUSYS which comprises with Cortex-Ax cores,CCI and GIC.

The external interrupts (outside MCUSYS) will feed through CIRQ and connect

to GIC in MCUSYS. When CIRQ is enabled, it will record the edge-sensitive

interrupts and generate a pulse signal to parent interrupt controller when

flush command is executed. With CIRQ, MCUSYS can be completely turned off

to improve the system power consumption without losing interrupts.



Required properties:

- compatible: should be one of

  - "mediatek,mt2701-cirq" for mt2701 CIRQ

  - "mediatek,mt8135-cirq" for mt8135 CIRQ

  - "mediatek,mt8173-cirq" for mt8173 CIRQ

  and "mediatek,cirq" as a fallback.

- interrupt-controller : Identifies the node as an interrupt controller.

- #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.

- reg: Physical base address of the cirq registers and length of memory

  mapped region.

- mediatek,ext-irq-range: Identifies external irq number range in different

  SOCs.



Example:

	cirq: interrupt-controller@10204000 {

		compatible = "mediatek,mt2701-cirq",

			     "mediatek,mtk-cirq";

		interrupt-controller;

		#interrupt-cells = <3>;

		interrupt-parent = <&sysirq>;

		reg = <0 0x10204000 0 0x400>;

		mediatek,ext-irq-start = <32 200>;

	};

Documentation/devicetree/bindings/interrupt-controller/mediatek,mtk-cirq.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/interrupt-controller/mediatek,mtk-cirq.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: MediaTek System Interrupt Controller



maintainers:

  - Youlin Pei <youlin.pei@mediatek.com>



description:

  In MediaTek SoCs, the CIRQ is a low power interrupt controller designed to

  work outside of MCUSYS which comprises with Cortex-Ax cores, CCI and GIC.

  The external interrupts (outside MCUSYS) will feed through CIRQ and connect

  to GIC in MCUSYS. When CIRQ is enabled, it will record the edge-sensitive

  interrupts and generate a pulse signal to parent interrupt controller when

  flush command is executed. With CIRQ, MCUSYS can be completely turned off

  to improve the system power consumption without losing interrupts.





properties:

  compatible:

    items:

      - enum:

          - mediatek,mt2701-cirq

          - mediatek,mt8135-cirq

          - mediatek,mt8173-cirq

          - mediatek,mt8192-cirq

      - const: mediatek,mtk-cirq



  reg:

    maxItems: 1



  '#interrupt-cells':

    const: 3



  interrupt-controller: true



  mediatek,ext-irq-range:

    $ref: /schemas/types.yaml#/definitions/uint32-array

    items:

      - description: First CIRQ interrupt

      - description: Last CIRQ interrupt

    description:

      Identifies the range of external interrupts in different SoCs



required:

  - compatible

  - reg

  - '#interrupt-cells'

  - interrupt-controller

  - mediatek,ext-irq-range



additionalProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/irq.h>



    cirq: interrupt-controller@10204000 {

        compatible = "mediatek,mt2701-cirq", "mediatek,mtk-cirq";

        reg = <0x10204000 0x400>;

        #interrupt-cells = <3>;

        interrupt-controller;

        interrupt-parent = <&sysirq>;

        mediatek,ext-irq-range = <32 200>;

    };

arch/loongarch/include/asm/irq.h

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@@ -93,7 +93,7 @@ int liointc_acpi_init(struct irq_domain *parent, 
int eiointc_acpi_init(struct irq_domain *parent,

					struct acpi_madt_eio_pic *acpi_eiointc);



struct irq_domain *htvec_acpi_init(struct irq_domain *parent,

int htvec_acpi_init(struct irq_domain *parent,

					struct acpi_madt_ht_pic *acpi_htvec);

int pch_lpc_acpi_init(struct irq_domain *parent,

					struct acpi_madt_lpc_pic *acpi_pchlpc);

drivers/acpi/pci_irq.c

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@@ -387,13 +387,15 @@ int acpi_pci_irq_enable(struct pci_dev *dev) 
	u8 pin;

	int triggering = ACPI_LEVEL_SENSITIVE;

	/*

	 * On ARM systems with the GIC interrupt model, level interrupts

	 * On ARM systems with the GIC interrupt model, or LoongArch

	 * systems with the LPIC interrupt model, level interrupts

	 * are always polarity high by specification; PCI legacy

	 * IRQs lines are inverted before reaching the interrupt

	 * controller and must therefore be considered active high

	 * as default.

	 */

	int polarity = acpi_irq_model == ACPI_IRQ_MODEL_GIC ?

	int polarity = acpi_irq_model == ACPI_IRQ_MODEL_GIC ||

		       acpi_irq_model == ACPI_IRQ_MODEL_LPIC ?

				      ACPI_ACTIVE_HIGH : ACPI_ACTIVE_LOW;

	char *link = NULL;

	char link_desc[16];