Commit 610cdf31 authored by Thierry Reding's avatar Thierry Reding
Browse files

arm64: tegra: Add MGBE nodes on Tegra234 



Add device tree nodes for the four instances of the Multi-Gigabit
Ethernet (MGBE) IP found on NVIDIA Tegra234 SoCs.

Signed-off-by: default avatarBhadram Varka <vbhadram@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 4f41e9d5

arch/arm64/boot/dts/nvidia/tegra234.dtsi

+136 −0
Original line number Diff line number Diff line
@@ -924,6 +924,142 @@ 
			#mbox-cells = <2>;

		};



		ethernet@6800000 {

			compatible = "nvidia,tegra234-mgbe";

			reg = <0x06800000 0x10000>,

			      <0x06810000 0x10000>,

			      <0x068a0000 0x10000>;

			reg-names = "hypervisor", "mac", "xpcs";

			interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "common";

			clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>,

				 <&bpmp TEGRA234_CLK_MGBE0_MAC>,

				 <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>,

				 <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>,

				 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>,

				 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>,

				 <&bpmp TEGRA234_CLK_MGBE0_TX>,

				 <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>,

				 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>,

				 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>,

				 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>,

				 <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>;

			clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",

				      "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",

				      "rx-pcs", "tx-pcs";

			resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>,

				 <&bpmp TEGRA234_RESET_MGBE0_PCS>;

			reset-names = "mac", "pcs";

			interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD &emc>,

					<&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>;

			interconnect-names = "dma-mem", "write";

			iommus = <&smmu_niso0 TEGRA234_SID_MGBE>;

			power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>;

			status = "disabled";

		};



		ethernet@6900000 {

			compatible = "nvidia,tegra234-mgbe";

			reg = <0x06900000 0x10000>,

			      <0x06910000 0x10000>,

			      <0x069a0000 0x10000>;

			reg-names = "hypervisor", "mac", "xpcs";

			interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "common";

			clocks = <&bpmp TEGRA234_CLK_MGBE1_APP>,

				 <&bpmp TEGRA234_CLK_MGBE1_MAC>,

				 <&bpmp TEGRA234_CLK_MGBE1_MAC_DIVIDER>,

				 <&bpmp TEGRA234_CLK_MGBE1_PTP_REF>,

				 <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT_M>,

				 <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT>,

				 <&bpmp TEGRA234_CLK_MGBE1_TX>,

				 <&bpmp TEGRA234_CLK_MGBE1_EEE_PCS>,

				 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_INPUT>,

				 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_M>,

				 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS>,

				 <&bpmp TEGRA234_CLK_MGBE1_TX_PCS>;

			clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",

				      "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",

				      "rx-pcs", "tx-pcs";

			resets = <&bpmp TEGRA234_RESET_MGBE1_MAC>,

				 <&bpmp TEGRA234_RESET_MGBE1_PCS>;

			reset-names = "mac", "pcs";

			interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEBRD &emc>,

					<&mc TEGRA234_MEMORY_CLIENT_MGBEBWR &emc>;

			interconnect-names = "dma-mem", "write";

			iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF1>;

			power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEB>;

			status = "disabled";

		};



		ethernet@6a00000 {

			compatible = "nvidia,tegra234-mgbe";

			reg = <0x06a00000 0x10000>,

			      <0x06a10000 0x10000>,

			      <0x06aa0000 0x10000>;

			reg-names = "hypervisor", "mac", "xpcs";

			interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "common";

			clocks = <&bpmp TEGRA234_CLK_MGBE2_APP>,

				 <&bpmp TEGRA234_CLK_MGBE2_MAC>,

				 <&bpmp TEGRA234_CLK_MGBE2_MAC_DIVIDER>,

				 <&bpmp TEGRA234_CLK_MGBE2_PTP_REF>,

				 <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT_M>,

				 <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT>,

				 <&bpmp TEGRA234_CLK_MGBE2_TX>,

				 <&bpmp TEGRA234_CLK_MGBE2_EEE_PCS>,

				 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_INPUT>,

				 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_M>,

				 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS>,

				 <&bpmp TEGRA234_CLK_MGBE2_TX_PCS>;

			clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",

				      "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",

				      "rx-pcs", "tx-pcs";

			resets = <&bpmp TEGRA234_RESET_MGBE2_MAC>,

				 <&bpmp TEGRA234_RESET_MGBE2_PCS>;

			reset-names = "mac", "pcs";

			interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBECRD &emc>,

					<&mc TEGRA234_MEMORY_CLIENT_MGBECWR &emc>;

			interconnect-names = "dma-mem", "write";

			iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF2>;

			power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEC>;

			status = "disabled";

		};



		ethernet@6b00000 {

			compatible = "nvidia,tegra234-mgbe";

			reg = <0x06b00000 0x10000>,

			      <0x06b10000 0x10000>,

			      <0x06ba0000 0x10000>;

			reg-names = "hypervisor", "mac", "xpcs";

			interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "common";

			clocks = <&bpmp TEGRA234_CLK_MGBE3_APP>,

				 <&bpmp TEGRA234_CLK_MGBE3_MAC>,

				 <&bpmp TEGRA234_CLK_MGBE3_MAC_DIVIDER>,

				 <&bpmp TEGRA234_CLK_MGBE3_PTP_REF>,

				 <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT_M>,

				 <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT>,

				 <&bpmp TEGRA234_CLK_MGBE3_TX>,

				 <&bpmp TEGRA234_CLK_MGBE3_EEE_PCS>,

				 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_INPUT>,

				 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_M>,

				 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS>,

				 <&bpmp TEGRA234_CLK_MGBE3_TX_PCS>;

			clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",

				      "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",

				      "rx-pcs", "tx-pcs";

			resets = <&bpmp TEGRA234_RESET_MGBE3_MAC>,

				 <&bpmp TEGRA234_RESET_MGBE3_PCS>;

			reset-names = "mac", "pcs";

			interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEDRD &emc>,

					<&mc TEGRA234_MEMORY_CLIENT_MGBEDWR &emc>;

			interconnect-names = "dma-mem", "write";

			iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF3>;

			power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>;

			status = "disabled";

		};



		smmu_niso1: iommu@8000000 {

			compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";

			reg = <0x8000000 0x1000000>,