spi: Convert spi-slave-mt27xx to json-schema

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/spi/mediatek,spi-slave-mt27xx.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: SPI Slave controller for MediaTek ARM SoCs

maintainers:

  - Leilk Liu <leilk.liu@mediatek.com>

allOf:

  - $ref: "/schemas/spi/spi-controller.yaml#"

properties:

  compatible:

    enum:

      - mediatek,mt2712-spi-slave

      - mediatek,mt8195-spi-slave

  reg:

    maxItems: 1

  interrupts:

    maxItems: 1

  clocks:

    maxItems: 1

  clock-names:

    items:

      - const: spi

required:

  - compatible

  - reg

  - interrupts

  - clocks

  - clock-names

unevaluatedProperties: false

examples:

  - |

    #include <dt-bindings/clock/mt2712-clk.h>

    #include <dt-bindings/gpio/gpio.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/interrupt-controller/irq.h>

    spi@10013000 {

      compatible = "mediatek,mt2712-spi-slave";

      reg = <0x10013000 0x100>;

      interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_LOW>;

      clocks = <&infracfg CLK_INFRA_AO_SPI1>;

      clock-names = "spi";

      assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>;

      assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;

    };

Binding for MTK SPI Slave controller

Required properties:

- compatible: should be one of the following.

    - mediatek,mt2712-spi-slave: for mt2712 platforms

    - mediatek,mt8195-spi-slave: for mt8195 platforms

- reg: Address and length of the register set for the device.

- interrupts: Should contain spi interrupt.

- clocks: phandles to input clocks.

  It's clock gate, and should be <&infracfg CLK_INFRA_AO_SPI1>.

- clock-names: should be "spi" for the clock gate.

Optional properties:

- assigned-clocks: it's mux clock, should be <&topckgen CLK_TOP_SPISLV_SEL>.

- assigned-clock-parents: parent of mux clock.

  It's PLL, and should be one of the following.

   -  <&topckgen CLK_TOP_UNIVPLL1_D2>: specify parent clock 312MHZ.

				       It's the default one.

   -  <&topckgen CLK_TOP_UNIVPLL1_D4>: specify parent clock 156MHZ.

   -  <&topckgen CLK_TOP_UNIVPLL2_D4>: specify parent clock 104MHZ.

   -  <&topckgen CLK_TOP_UNIVPLL1_D8>: specify parent clock 78MHZ.

Example:

- SoC Specific Portion:

spis1: spi@10013000 {

	compatible = "mediatek,mt2712-spi-slave";

	reg = <0 0x10013000 0 0x100>;

	interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_LOW>;

	clocks = <&infracfg CLK_INFRA_AO_SPI1>;

	clock-names = "spi";

	assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>;

	assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;

};