Commit 60cfad32 authored by Kenneth Feng's avatar Kenneth Feng Committed by Alex Deucher
Browse files

drm/amd/pm: enable mode1 reset on smu_v13_0_10 



enable mode1 reset and prioritize debug port on smu_v13_0_10
as a more reliable message processing

v2 - move mode1 reset callback to smu_v13_0_0_ppt.c

Signed-off-by: default avatarKenneth Feng <kenneth.feng@amd.com>
Reviewed-by: default avatarYang Wang <kevinyang.wang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 4cc16d64

drivers/gpu/drm/amd/amdgpu/soc21.c

+1 −0
Original line number Diff line number Diff line
@@ -322,6 +322,7 @@ soc21_asic_reset_method(struct amdgpu_device *adev) 
	switch (adev->ip_versions[MP1_HWIP][0]) {

	case IP_VERSION(13, 0, 0):

	case IP_VERSION(13, 0, 7):

	case IP_VERSION(13, 0, 10):

		return AMD_RESET_METHOD_MODE1;

	case IP_VERSION(13, 0, 4):

		return AMD_RESET_METHOD_MODE2;

drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h

+4 −0
Original line number Diff line number Diff line
@@ -568,6 +568,10 @@ struct smu_context 
	u32 param_reg;

	u32 msg_reg;

	u32 resp_reg;



	u32 debug_param_reg;

	u32 debug_msg_reg;

	u32 debug_resp_reg;

};



struct i2c_adapter;

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

+51 −2
Original line number Diff line number Diff line
@@ -70,6 +70,26 @@ 


#define MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE	0x4000



#define mmMP1_SMN_C2PMSG_66                                                                            0x0282

#define mmMP1_SMN_C2PMSG_66_BASE_IDX                                                                   0



#define mmMP1_SMN_C2PMSG_82                                                                            0x0292

#define mmMP1_SMN_C2PMSG_82_BASE_IDX                                                                   0



#define mmMP1_SMN_C2PMSG_90                                                                            0x029a

#define mmMP1_SMN_C2PMSG_90_BASE_IDX                                                                   0



#define mmMP1_SMN_C2PMSG_75                                                                            0x028b

#define mmMP1_SMN_C2PMSG_75_BASE_IDX                                                                   0



#define mmMP1_SMN_C2PMSG_53                                                                            0x0275

#define mmMP1_SMN_C2PMSG_53_BASE_IDX                                                                   0



#define mmMP1_SMN_C2PMSG_54                                                                            0x0276

#define mmMP1_SMN_C2PMSG_54_BASE_IDX                                                                   0



#define DEBUGSMC_MSG_Mode1Reset	2



static struct cmn2asic_msg_mapping smu_v13_0_0_message_map[SMU_MSG_MAX_COUNT] = {

	MSG_MAP(TestMessage,			PPSMC_MSG_TestMessage,                 1),

	MSG_MAP(GetSmuVersion,			PPSMC_MSG_GetSmuVersion,               1),
@@ -1763,6 +1783,35 @@ static int smu_v13_0_0_set_df_cstate(struct smu_context *smu, 
					       NULL);

}



static int smu_v13_0_0_mode1_reset(struct smu_context *smu)

{

	int ret;

	struct amdgpu_device *adev = smu->adev;



	if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 10))

		ret = smu_cmn_send_debug_smc_msg(smu, DEBUGSMC_MSG_Mode1Reset);

	else

		ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);



	if (!ret)

		msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);



	return ret;

}



static void smu_v13_0_0_set_smu_mailbox_registers(struct smu_context *smu)

{

	struct amdgpu_device *adev = smu->adev;



	smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);

	smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);

	smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);



	smu->debug_param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_53);

	smu->debug_msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_75);

	smu->debug_resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_54);

}



static const struct pptable_funcs smu_v13_0_0_ppt_funcs = {

	.get_allowed_feature_mask = smu_v13_0_0_get_allowed_feature_mask,

	.set_default_dpm_table = smu_v13_0_0_set_default_dpm_table,
@@ -1830,7 +1879,7 @@ static const struct pptable_funcs smu_v13_0_0_ppt_funcs = { 
	.baco_enter = smu_v13_0_baco_enter,

	.baco_exit = smu_v13_0_baco_exit,

	.mode1_reset_is_support = smu_v13_0_0_is_mode1_reset_supported,

	.mode1_reset = smu_v13_0_mode1_reset,

	.mode1_reset = smu_v13_0_0_mode1_reset,

	.set_mp1_state = smu_v13_0_0_set_mp1_state,

	.set_df_cstate = smu_v13_0_0_set_df_cstate,

};
@@ -1844,5 +1893,5 @@ void smu_v13_0_0_set_ppt_funcs(struct smu_context *smu) 
	smu->table_map = smu_v13_0_0_table_map;

	smu->pwr_src_map = smu_v13_0_0_pwr_src_map;

	smu->workload_map = smu_v13_0_0_workload_map;

	smu_v13_0_set_smu_mailbox_registers(smu);

	smu_v13_0_0_set_smu_mailbox_registers(smu);

}

drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c

+18 −0
Original line number Diff line number Diff line
@@ -233,6 +233,18 @@ static void __smu_cmn_send_msg(struct smu_context *smu, 
	WREG32(smu->msg_reg, msg);

}



static int __smu_cmn_send_debug_msg(struct smu_context *smu,

			       u32 msg,

			       u32 param)

{

	struct amdgpu_device *adev = smu->adev;



	WREG32(smu->debug_param_reg, param);

	WREG32(smu->debug_msg_reg, msg);

	WREG32(smu->debug_resp_reg, 0);



	return 0;

}

/**

 * smu_cmn_send_msg_without_waiting -- send the message; don't wait for status

 * @smu: pointer to an SMU context
@@ -386,6 +398,12 @@ int smu_cmn_send_smc_msg(struct smu_context *smu, 
					       read_arg);

}



int smu_cmn_send_debug_smc_msg(struct smu_context *smu,

			 uint32_t msg)

{

	return __smu_cmn_send_debug_msg(smu, msg, 0);

}



int smu_cmn_to_asic_specific_index(struct smu_context *smu,

				   enum smu_cmn2asic_mapping_type type,

				   uint32_t index)

drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h

+3 −0
Original line number Diff line number Diff line
@@ -42,6 +42,9 @@ int smu_cmn_send_smc_msg(struct smu_context *smu, 
			 enum smu_message_type msg,

			 uint32_t *read_arg);



int smu_cmn_send_debug_smc_msg(struct smu_context *smu,

			 uint32_t msg);



int smu_cmn_wait_for_response(struct smu_context *smu);



int smu_cmn_to_asic_specific_index(struct smu_context *smu,