Commit 60ac35bf authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'irq-core-2022-10-12' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull interrupt updates from Thomas Gleixner:
 "Core code:

   - Provide a generic wrapper which can be utilized in drivers to
     handle the problem of force threaded demultiplex interrupts on RT
     enabled kernels. This avoids conditionals and horrible quirks in
     drivers all over the place

   - Fix up affected pinctrl and GPIO drivers to make them cleanly RT
     safe

  Interrupt drivers:

   - A new driver for the FSL MU platform specific MSI implementation

   - Make irqchip_init() available for pure ACPI based systems

   - Provide a functional DT binding for the Realtek RTL interrupt chip

   - The usual DT updates and small code improvements all over the
     place"

* tag 'irq-core-2022-10-12' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (21 commits)
  irqchip: IMX_MU_MSI should depend on ARCH_MXC
  irqchip/imx-mu-msi: Fix wrong register offset for 8ulp
  irqchip/ls-extirq: Fix invalid wait context by avoiding to use regmap
  dt-bindings: irqchip: Describe the IMX MU block as a MSI controller
  irqchip: Add IMX MU MSI controller driver
  dt-bindings: irqchip: renesas,irqc: Add r8a779g0 support
  irqchip/gic-v3: Fix typo in comment
  dt-bindings: interrupt-controller: ti,sci-intr: Fix missing reg property in the binding
  dt-bindings: irqchip: ti,sci-inta: Fix warning for missing #interrupt-cells
  irqchip: Allow extra fields to be passed to IRQCHIP_PLATFORM_DRIVER_END
  platform-msi: Export symbol platform_msi_create_irq_domain()
  irqchip/realtek-rtl: use parent interrupts
  dt-bindings: interrupt-controller: realtek,rtl-intc: require parents
  irqchip/realtek-rtl: use irq_domain_add_linear()
  irqchip: Make irqchip_init() usable on pure ACPI systems
  bcma: gpio: Use generic_handle_irq_safe()
  gpio: mlxbf2: Use generic_handle_irq_safe()
  platform/x86: intel_int0002_vgpio: Use generic_handle_irq_safe()
  ssb: gpio: Use generic_handle_irq_safe()
  pinctrl: amd: Use generic_handle_irq_safe()
  ...
parents 49da0700 b8d49bcd

Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/interrupt-controller/fsl,mu-msi.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Freescale/NXP i.MX Messaging Unit (MU) work as msi controller



maintainers:

  - Frank Li <Frank.Li@nxp.com>



description: |

  The Messaging Unit module enables two processors within the SoC to

  communicate and coordinate by passing messages (e.g. data, status

  and control) through the MU interface. The MU also provides the ability

  for one processor (A side) to signal the other processor (B side) using

  interrupts.



  Because the MU manages the messaging between processors, the MU uses

  different clocks (from each side of the different peripheral buses).

  Therefore, the MU must synchronize the accesses from one side to the

  other. The MU accomplishes synchronization using two sets of matching

  registers (Processor A-side, Processor B-side).



  MU can work as msi interrupt controller to do doorbell



allOf:

  - $ref: /schemas/interrupt-controller/msi-controller.yaml#



properties:

  compatible:

    enum:

      - fsl,imx6sx-mu-msi

      - fsl,imx7ulp-mu-msi

      - fsl,imx8ulp-mu-msi

      - fsl,imx8ulp-mu-msi-s4



  reg:

    items:

      - description: a side register base address

      - description: b side register base address



  reg-names:

    items:

      - const: processor-a-side

      - const: processor-b-side



  interrupts:

    description: a side interrupt number.

    maxItems: 1



  clocks:

    maxItems: 1



  power-domains:

    items:

      - description: a side power domain

      - description: b side power domain



  power-domain-names:

    items:

      - const: processor-a-side

      - const: processor-b-side



  interrupt-controller: true



  msi-controller: true



  "#msi-cells":

    const: 0



required:

  - compatible

  - reg

  - interrupts

  - interrupt-controller

  - msi-controller

  - "#msi-cells"



additionalProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/firmware/imx/rsrc.h>



    msi-controller@5d270000 {

        compatible = "fsl,imx6sx-mu-msi";

        msi-controller;

        #msi-cells = <0>;

        interrupt-controller;

        reg = <0x5d270000 0x10000>,     /* A side */

              <0x5d300000 0x10000>;     /* B side */

        reg-names = "processor-a-side", "processor-b-side";

        interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;

        power-domains = <&pd IMX_SC_R_MU_12A>,

                        <&pd IMX_SC_R_MU_12B>;

        power-domain-names = "processor-a-side", "processor-b-side";

    };

Documentation/devicetree/bindings/interrupt-controller/realtek,rtl-intc.yaml

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@@ -6,6 +6,14 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# 


title: Realtek RTL SoC interrupt controller devicetree bindings



description:

  Interrupt controller and router for Realtek MIPS SoCs, allowing each SoC

  interrupt to be routed to one parent CPU (hardware) interrupt, or left

  disconnected.

  All connected input lines from SoC peripherals can be masked individually,

  and an interrupt status register is present to indicate which interrupts are

  pending.



maintainers:

  - Birger Koblitz <mail@birger-koblitz.de>

  - Bert Vermeulen <bert@biot.com>
@@ -13,23 +21,33 @@ maintainers: 


properties:

  compatible:

    const: realtek,rtl-intc

    oneOf:

      - items:

          - enum:

              - realtek,rtl8380-intc

          - const: realtek,rtl-intc

      - const: realtek,rtl-intc

        deprecated: true



  "#interrupt-cells":

    description:

      SoC interrupt line index.

    const: 1



  reg:

    maxItems: 1



  interrupts:

    maxItems: 1

    minItems: 1

    maxItems: 15

    description:

      List of parent interrupts, in the order that they are connected to this

      interrupt router's outputs, starting at the first output.



  interrupt-controller: true



  "#address-cells":

    const: 0



  interrupt-map:

    deprecated: true

    description: Describes mapping from SoC interrupts to CPU interrupts



required:
@@ -37,21 +55,33 @@ required: 
  - reg

  - "#interrupt-cells"

  - interrupt-controller



allOf:

  - if:

      properties:

        compatible:

          const: realtek,rtl-intc

    then:

      properties:

        "#address-cells":

          const: 0

      required:

        - "#address-cells"

        - interrupt-map

    else:

      required:

        - interrupts



additionalProperties: false



examples:

  - |

    intc: interrupt-controller@3000 {

      compatible = "realtek,rtl-intc";

    interrupt-controller@3000 {

      compatible = "realtek,rtl8380-intc", "realtek,rtl-intc";

      #interrupt-cells = <1>;

      interrupt-controller;

      reg = <0x3000 0x20>;

      #address-cells = <0>;

      interrupt-map =

              <31 &cpuintc 2>,

              <30 &cpuintc 1>,

              <29 &cpuintc 5>;

      reg = <0x3000 0x18>;



      interrupt-parent = <&cpuintc>;

      interrupts = <2>, <3>, <4>, <5>, <6>;

    };

Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.yaml

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@@ -37,6 +37,7 @@ properties: 
          - renesas,intc-ex-r8a77990    # R-Car E3

          - renesas,intc-ex-r8a77995    # R-Car D3

          - renesas,intc-ex-r8a779a0    # R-Car V3U

          - renesas,intc-ex-r8a779g0    # R-Car V4H

      - const: renesas,irqc



  '#interrupt-cells':

Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.yaml

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@@ -59,6 +59,9 @@ properties: 


  interrupt-controller: true



  '#interrupt-cells':

    const: 0



  msi-controller: true



  ti,interrupt-ranges:

Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.yaml

+3 −0
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@@ -58,6 +58,9 @@ properties: 
        1 = If intr supports edge triggered interrupts.

        4 = If intr supports level triggered interrupts.



  reg:

    maxItems: 1



  interrupt-controller: true



  '#interrupt-cells':