Commit 60aac460 authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher
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drm/amd/pm: correct UMD pstate clocks for Dimgrey Cavefish and Beige Goby 



Correct the UMD pstate profiling clocks for Dimgrey Cavefish and Beige
Goby.

Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c8cb19c7

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

+21 −5
Original line number Diff line number Diff line
@@ -1231,21 +1231,37 @@ static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu) 
				&dpm_context->dpm_tables.soc_table;

	struct smu_umd_pstate_table *pstate_table =

				&smu->pstate_table;

	struct amdgpu_device *adev = smu->adev;



	pstate_table->gfxclk_pstate.min = gfx_table->min;

	pstate_table->gfxclk_pstate.peak = gfx_table->max;

	if (gfx_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK)

		pstate_table->gfxclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK;



	pstate_table->uclk_pstate.min = mem_table->min;

	pstate_table->uclk_pstate.peak = mem_table->max;

	if (mem_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK)

		pstate_table->uclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK;



	pstate_table->socclk_pstate.min = soc_table->min;

	pstate_table->socclk_pstate.peak = soc_table->max;

	if (soc_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK)



	switch (adev->asic_type) {

	case CHIP_SIENNA_CICHLID:

	case CHIP_NAVY_FLOUNDER:

		pstate_table->gfxclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK;

		pstate_table->uclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK;

		pstate_table->socclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK;

		break;

	case CHIP_DIMGREY_CAVEFISH:

		pstate_table->gfxclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_GFXCLK;

		pstate_table->uclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_MEMCLK;

		pstate_table->socclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_SOCCLK;

		break;

	case CHIP_BEIGE_GOBY:

		pstate_table->gfxclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_GFXCLK;

		pstate_table->uclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_MEMCLK;

		pstate_table->socclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_SOCCLK;

		break;

	default:

		break;

	}



	return 0;

}

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.h

+8 −0
Original line number Diff line number Diff line
@@ -33,6 +33,14 @@ typedef enum { 
#define SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK    960

#define SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK    1000



#define DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_GFXCLK 1950

#define DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_SOCCLK 960

#define DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_MEMCLK 676



#define BEIGE_GOBY_UMD_PSTATE_PROFILING_GFXCLK 2200

#define BEIGE_GOBY_UMD_PSTATE_PROFILING_SOCCLK 960

#define BEIGE_GOBY_UMD_PSTATE_PROFILING_MEMCLK 1000



extern void sienna_cichlid_set_ppt_funcs(struct smu_context *smu);



#endif