Commit 6087623e authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Rob Clark
Browse files

drm/msm/dpu: don't clear IRQ register twice 



We already clear the IRQ status register before processing IRQs, so do
not clear the register again. Especially do not clear the IRQ status
_after_ processing the IRQ as this way we can loose the event.

Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarAbhinav Kumar <abhinavk@codeaurora.org>
Link: https://lore.kernel.org/r/20210617222029.463045-3-dmitry.baryshkov@linaro.org


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent a7303361

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

+0 −17
Original line number Diff line number Diff line
@@ -120,21 +120,6 @@ static const struct dpu_intr_reg dpu_intr_set[] = { 
#define DPU_IRQ_REG(irq_idx)	(irq_idx / 32)

#define DPU_IRQ_MASK(irq_idx)	(BIT(irq_idx % 32))



static void dpu_hw_intr_clear_intr_status_nolock(struct dpu_hw_intr *intr,

		int irq_idx)

{

	int reg_idx;



	if (!intr)

		return;



	reg_idx = DPU_IRQ_REG(irq_idx);

	DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off, DPU_IRQ_MASK(irq_idx));



	/* ensure register writes go through */

	wmb();

}



/**

 * dpu_core_irq_callback_handler - dispatch core interrupts

 * @arg:		private data of callback handler
@@ -203,8 +188,6 @@ irqreturn_t dpu_core_irq(struct dpu_kms *dpu_kms) 


			dpu_core_irq_callback_handler(dpu_kms, irq_idx);



			dpu_hw_intr_clear_intr_status_nolock(intr, irq_idx);



			/*

			 * When callback finish, clear the irq_status

			 * with the matching mask. Once irq_status