Unverified Commit 60769662 authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
Browse files

!11186 Backport bugfix for AMD SMN 

Merge Pull Request from: @ci-robot 
 
PR sync from: Wei Li <liwei391@huawei.com>
https://mailweb.openeuler.org/hyperkitty/list/kernel@openeuler.org/message/NU5HHVSGFMT2YEG7M4ZPS76N7GHD24XO/ 
Backport bugfix for AMD SMN.

Naveen Naidu (1):
  PCI: Add PCI_ERROR_RESPONSE and related definitions

Yazen Ghannam (1):
  x86/amd_nb: Check for invalid SMN reads


-- 
2.25.1
 
https://gitee.com/openeuler/kernel/issues/IAMTH9 
 
Link:https://gitee.com/openeuler/kernel/pulls/11186

 

Reviewed-by: default avatarXie XiuQi <xiexiuqi@huawei.com>
Reviewed-by: default avatarLiu YongQiang <liuyongqiang13@huawei.com>
Signed-off-by: default avatarZhang Changzhong <zhangchangzhong@huawei.com>
parents 022a9b79 028c6f11

arch/x86/kernel/amd_nb.c

+8 −1
Original line number Diff line number Diff line
@@ -173,7 +173,14 @@ static int __amd_smn_rw(u16 node, u32 address, u32 *value, bool write) 


int amd_smn_read(u16 node, u32 address, u32 *value)

{

	return __amd_smn_rw(node, address, value, false);

	int err = __amd_smn_rw(node, address, value, false);



	if (PCI_POSSIBLE_ERROR(*value)) {

		err = -ENODEV;

		*value = 0;

	}



	return err;

}

EXPORT_SYMBOL_GPL(amd_smn_read);

include/linux/pci.h

+9 −0
Original line number Diff line number Diff line
@@ -124,6 +124,15 @@ enum pci_interrupt_pin { 
/* The number of legacy PCI INTx interrupts */

#define PCI_NUM_INTX	4



/*

 * Reading from a device that doesn't respond typically returns ~0.  A

 * successful read from a device may also return ~0, so you need additional

 * information to reliably identify errors.

 */

#define PCI_ERROR_RESPONSE		(~0ULL)

#define PCI_SET_ERROR_RESPONSE(val)	(*(val) = ((typeof(*(val))) PCI_ERROR_RESPONSE))

#define PCI_POSSIBLE_ERROR(val)		((val) == ((typeof(val)) PCI_ERROR_RESPONSE))



/*

 * pci_power_t values must match the bits in the Capabilities PME_Support

 * and Control/Status PowerState fields in the Power Management capability.