Commit 60657fb9 authored by Srinivasa Rao Mandadapu's avatar Srinivasa Rao Mandadapu Committed by Vinod Koul
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dt-bindings: soundwire: qcom: Add bindings for audio clock reset control property 



Update description for audio clock reset control property, which is required
for latest chipsets, to allow rx, tx and wsa bus clock enabling in software
 control mode by configuring dynamic clock gating control registers.

Signed-off-by: default avatarSrinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Co-developed-by: default avatarVenkata Prasad Potturu <quic_potturu@quicinc.com>
Signed-off-by: default avatarVenkata Prasad Potturu <quic_potturu@quicinc.com>
Reviewed-by: default avatarStephen Boyd <swboyd@chromium.org>
Acked-by: default avatarRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1646316128-21082-3-git-send-email-quic_srivasam@quicinc.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent d6de188a

Documentation/devicetree/bindings/soundwire/qcom,sdw.txt

+14 −0
Original line number Diff line number Diff line
@@ -162,6 +162,18 @@ board specific bus parameters. 
		    or applicable for the respective data port.

		    More info in MIPI Alliance SoundWire 1.0 Specifications.



- reset:

	Usage: optional

	Value type: <prop-encoded-array>

	Definition: Should specify the SoundWire audio CSR reset controller interface,

		    which is required for SoundWire version 1.6.0 and above.



- reset-names:

	Usage: optional

	Value type: <stringlist>

	Definition: should be "swr_audio_cgcr" for SoundWire audio CSR reset

		    controller interface.



Note:

	More Information on detail of encoding of these fields can be

found in MIPI Alliance SoundWire 1.0 Specifications.
@@ -180,6 +192,8 @@ soundwire: soundwire@c85 { 
	interrupts = <20 IRQ_TYPE_EDGE_RISING>;

	clocks = <&wcc>;

	clock-names = "iface";

	resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>;

	reset-names = "swr_audio_cgcr";

	#sound-dai-cells = <1>;

	qcom,dports-type = <0>;

	qcom,dout-ports	= <6>;