Commit 60477435 authored by Konrad Dybcio's avatar Konrad Dybcio Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: sm8350: Add SDHCI2 



Add and configure the SDHCI host responsible for (mostly) SD Card and
its corresponding pins' sleep states.

The setup is *literally* 1:1 with 8450 (bar SDR50/104 may not be
broken).

Signed-off-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221116123612.34302-2-konrad.dybcio@linaro.org
parent 25f08f02

arch/arm64/boot/dts/qcom/sm8350.dtsi

+79 −0
Original line number Diff line number Diff line
@@ -1761,6 +1761,46 @@ 
			gpio-ranges = <&tlmm 0 0 204>;

			wakeup-parent = <&pdc>;



			sdc2_default_state: sdc2-default-state {

				clk-pins {

					pins = "sdc2_clk";

					drive-strength = <16>;

					bias-disable;

				};



				cmd-pins {

					pins = "sdc2_cmd";

					drive-strength = <16>;

					bias-pull-up;

				};



				data-pins {

					pins = "sdc2_data";

					drive-strength = <16>;

					bias-pull-up;

				};

			};



			sdc2_sleep_state: sdc2-sleep-state {

				clk-pins {

					pins = "sdc2_clk";

					drive-strength = <2>;

					bias-disable;

				};



				cmd-pins {

					pins = "sdc2_cmd";

					drive-strength = <2>;

					bias-pull-up;

				};



				data-pins {

					pins = "sdc2_data";

					drive-strength = <2>;

					bias-pull-up;

				};

			};



			qup_uart3_default_state: qup-uart3-default-state {

				rx-pins {

					pins = "gpio18";
@@ -2329,6 +2369,45 @@ 
			};

		};



		sdhc_2: sdhci@8804000 {

			compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5";

			reg = <0 0x08804000 0 0x1000>;



			interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "hc_irq", "pwr_irq";



			clocks = <&gcc GCC_SDCC2_AHB_CLK>,

				 <&gcc GCC_SDCC2_APPS_CLK>,

				 <&rpmhcc RPMH_CXO_CLK>;

			clock-names = "iface", "core", "xo";

			resets = <&gcc GCC_SDCC2_BCR>;

			interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,

					<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;

			interconnect-names = "sdhc-ddr","cpu-sdhc";

			iommus = <&apps_smmu 0x4a0 0x0>;

			power-domains = <&rpmhpd SM8350_CX>;

			operating-points-v2 = <&sdhc2_opp_table>;

			bus-width = <4>;

			dma-coherent;



			status = "disabled";



			sdhc2_opp_table: opp-table {

				compatible = "operating-points-v2";



				opp-100000000 {

					opp-hz = /bits/ 64 <100000000>;

					required-opps = <&rpmhpd_opp_low_svs>;

				};



				opp-202000000 {

					opp-hz = /bits/ 64 <202000000>;

					required-opps = <&rpmhpd_opp_svs_l1>;

				};

			};

		};



		usb_1_hsphy: phy@88e3000 {

			compatible = "qcom,sm8350-usb-hs-phy",

				     "qcom,usb-snps-hs-7nm-phy";