Commit 6044144b authored by Hugo Villeneuve's avatar Hugo Villeneuve Committed by Gu Bowen
Browse files

serial: sc16is7xx: fix invalid FIFO access with special register set 

mainline inclusion
from mainline-v6.11-rc3
commit 7d3b793faaab1305994ce568b59d61927235f57b
category: bugfix
bugzilla: https://gitee.com/src-openeuler/kernel/issues/IAOY1A
CVE: CVE-2024-44950

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=7d3b793faaab1305994ce568b59d61927235f57b



--------------------------------

When enabling access to the special register set, Receiver time-out and
RHR interrupts can happen. In this case, the IRQ handler will try to read
from the FIFO thru the RHR register at address 0x00, but address 0x00 is
mapped to DLL register, resulting in erroneous FIFO reading.

Call graph example:
    sc16is7xx_startup(): entry
    sc16is7xx_ms_proc(): entry
    sc16is7xx_set_termios(): entry
    sc16is7xx_set_baud(): DLH/DLL = $009C --> access special register set
    sc16is7xx_port_irq() entry            --> IIR is 0x0C
    sc16is7xx_handle_rx() entry
    sc16is7xx_fifo_read(): --> unable to access FIFO (RHR) because it is
                               mapped to DLL (LCR=LCR_CONF_MODE_A)
    sc16is7xx_set_baud(): exit --> Restore access to general register set

Fix the problem by claiming the efr_lock mutex when accessing the Special
register set.

Fixes: dfeae619 ("serial: sc16is7xx")
Cc: stable@vger.kernel.org
Signed-off-by: default avatarHugo Villeneuve <hvilleneuve@dimonoff.com>
Link: https://lore.kernel.org/r/20240723125302.1305372-3-hugo@hugovil.com


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Conflicts:
	drivers/tty/serial/sc16is7xx.c
[Trace context conflict, no adaptation required.]
Signed-off-by: default avatarGu Bowen <gubowen5@huawei.com>
parent 91ff8f4b

drivers/tty/serial/sc16is7xx.c

+4 −0
Original line number Diff line number Diff line
@@ -545,6 +545,8 @@ static int sc16is7xx_set_baud(struct uart_port *port, int baud) 
			      SC16IS7XX_MCR_CLKSEL_BIT,

			      prescaler == 1 ? 0 : SC16IS7XX_MCR_CLKSEL_BIT);



	mutex_lock(&one->efr_lock);



	/* Open the LCR divisors for configuration */

	sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,

			     SC16IS7XX_LCR_CONF_MODE_A);
@@ -558,6 +560,8 @@ static int sc16is7xx_set_baud(struct uart_port *port, int baud) 
	/* Put LCR back to the normal mode */

	sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);



	mutex_unlock(&one->efr_lock);



	return DIV_ROUND_CLOSEST((clk / prescaler) / 16, div);

}