Commit 60417a0d authored by Max Filippov's avatar Max Filippov Committed by sanglipeng
Browse files

xtensa: PMU: fix base address for the newer hardware 

stable inclusion
from stable-v5.10.195
commit b24bebcea55693c35cff5a4398802d1c18aeb340
category: bugfix
bugzilla: https://gitee.com/openeuler/kernel/issues/I95JOC

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=b24bebcea55693c35cff5a4398802d1c18aeb340



--------------------------------

commit 687eb3c4 upstream.

With introduction of ERI access control in RG.0 base address of the PMU
unit registers has changed. Add support for the new PMU configuration.

Cc: stable@vger.kernel.org
Signed-off-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: default avatarsanglipeng <sanglipeng1@jd.com>
parent bbe580c8

arch/xtensa/include/asm/core.h

+9 −0
Original line number Diff line number Diff line
@@ -26,4 +26,13 @@ 
#define XCHAL_SPANNING_WAY 0

#endif



#ifndef XCHAL_HW_MIN_VERSION

#if defined(XCHAL_HW_MIN_VERSION_MAJOR) && defined(XCHAL_HW_MIN_VERSION_MINOR)

#define XCHAL_HW_MIN_VERSION (XCHAL_HW_MIN_VERSION_MAJOR * 100 + \

			      XCHAL_HW_MIN_VERSION_MINOR)

#else

#define XCHAL_HW_MIN_VERSION 0

#endif

#endif



#endif

arch/xtensa/kernel/perf_event.c

+13 −4
Original line number Diff line number Diff line
@@ -13,17 +13,26 @@ 
#include <linux/perf_event.h>

#include <linux/platform_device.h>



#include <asm/core.h>

#include <asm/processor.h>

#include <asm/stacktrace.h>



#define XTENSA_HWVERSION_RG_2015_0	260000



#if XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RG_2015_0

#define XTENSA_PMU_ERI_BASE		0x00101000

#else

#define XTENSA_PMU_ERI_BASE		0x00001000

#endif



/* Global control/status for all perf counters */

#define XTENSA_PMU_PMG			0x1000

#define XTENSA_PMU_PMG			XTENSA_PMU_ERI_BASE

/* Perf counter values */

#define XTENSA_PMU_PM(i)		(0x1080 + (i) * 4)

#define XTENSA_PMU_PM(i)		(XTENSA_PMU_ERI_BASE + 0x80 + (i) * 4)

/* Perf counter control registers */

#define XTENSA_PMU_PMCTRL(i)		(0x1100 + (i) * 4)

#define XTENSA_PMU_PMCTRL(i)		(XTENSA_PMU_ERI_BASE + 0x100 + (i) * 4)

/* Perf counter status registers */

#define XTENSA_PMU_PMSTAT(i)		(0x1180 + (i) * 4)

#define XTENSA_PMU_PMSTAT(i)		(XTENSA_PMU_ERI_BASE + 0x180 + (i) * 4)



#define XTENSA_PMU_PMG_PMEN		0x1