Commit 603d11c4 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'hns3-next' 



Huazhong Tan says:

====================
net: hns3: updates for -next

To facilitate code maintenance and compatibility, #1 and #2 add
device version to replace pci revision, #3 to #9 adds support for
querying device capabilities and specifications, then the driver
can use these query results to implement corresponding features
(some features will be implemented later).

And #10 is a minor cleanup since too many parameters for
hclge_shaper_para_calc().
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 090bc03b ff7e4d0d

drivers/net/ethernet/hisilicon/hns3/hnae3.h

+77 −4
Original line number Diff line number Diff line
@@ -34,6 +34,13 @@ 


#define HNAE3_MIN_VECTOR_NUM	2 /* first one for misc, another for IO */



/* Device version */

#define HNAE3_DEVICE_VERSION_V1   0x00020

#define HNAE3_DEVICE_VERSION_V2   0x00021

#define HNAE3_DEVICE_VERSION_V3   0x00030



#define HNAE3_PCI_REVISION_BIT_SIZE		8



/* Device IDs */

#define HNAE3_DEV_ID_GE				0xA220

#define HNAE3_DEV_ID_25GE			0xA221
@@ -54,8 +61,6 @@ 
#define HNAE3_KNIC_CLIENT_INITED_B		0x3

#define HNAE3_UNIC_CLIENT_INITED_B		0x4

#define HNAE3_ROCE_CLIENT_INITED_B		0x5

#define HNAE3_DEV_SUPPORT_FD_B			0x6

#define HNAE3_DEV_SUPPORT_GRO_B			0x7



#define HNAE3_DEV_SUPPORT_ROCE_DCB_BITS (BIT(HNAE3_DEV_SUPPORT_DCB_B) |\

		BIT(HNAE3_DEV_SUPPORT_ROCE_B))
@@ -66,11 +71,64 @@ 
#define hnae3_dev_dcb_supported(hdev) \

	hnae3_get_bit((hdev)->ae_dev->flag, HNAE3_DEV_SUPPORT_DCB_B)



enum HNAE3_DEV_CAP_BITS {

	HNAE3_DEV_SUPPORT_FD_B,

	HNAE3_DEV_SUPPORT_GRO_B,

	HNAE3_DEV_SUPPORT_FEC_B,

	HNAE3_DEV_SUPPORT_UDP_GSO_B,

	HNAE3_DEV_SUPPORT_QB_B,

	HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B,

	HNAE3_DEV_SUPPORT_PTP_B,

	HNAE3_DEV_SUPPORT_INT_QL_B,

	HNAE3_DEV_SUPPORT_SIMPLE_BD_B,

	HNAE3_DEV_SUPPORT_TX_PUSH_B,

	HNAE3_DEV_SUPPORT_PHY_IMP_B,

	HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B,

	HNAE3_DEV_SUPPORT_HW_PAD_B,

	HNAE3_DEV_SUPPORT_STASH_B,

};



#define hnae3_dev_fd_supported(hdev) \

	hnae3_get_bit((hdev)->ae_dev->flag, HNAE3_DEV_SUPPORT_FD_B)

	test_bit(HNAE3_DEV_SUPPORT_FD_B, (hdev)->ae_dev->caps)



#define hnae3_dev_gro_supported(hdev) \

	hnae3_get_bit((hdev)->ae_dev->flag, HNAE3_DEV_SUPPORT_GRO_B)

	test_bit(HNAE3_DEV_SUPPORT_GRO_B, (hdev)->ae_dev->caps)



#define hnae3_dev_fec_supported(hdev) \

	test_bit(HNAE3_DEV_SUPPORT_FEC_B, (hdev)->ae_dev->caps)



#define hnae3_dev_udp_gso_supported(hdev) \

	test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, (hdev)->ae_dev->caps)



#define hnae3_dev_qb_supported(hdev) \

	test_bit(HNAE3_DEV_SUPPORT_QB_B, (hdev)->ae_dev->caps)



#define hnae3_dev_fd_forward_tc_supported(hdev) \

	test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, (hdev)->ae_dev->caps)



#define hnae3_dev_ptp_supported(hdev) \

	test_bit(HNAE3_DEV_SUPPORT_PTP_B, (hdev)->ae_dev->caps)



#define hnae3_dev_int_ql_supported(hdev) \

	test_bit(HNAE3_DEV_SUPPORT_INT_QL_B, (hdev)->ae_dev->caps)



#define hnae3_dev_simple_bd_supported(hdev) \

	test_bit(HNAE3_DEV_SUPPORT_SIMPLE_BD_B, (hdev)->ae_dev->caps)



#define hnae3_dev_tx_push_supported(hdev) \

	test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, (hdev)->ae_dev->caps)



#define hnae3_dev_phy_imp_supported(hdev) \

	test_bit(HNAE3_DEV_SUPPORT_PHY_IMP_B, (hdev)->ae_dev->caps)



#define hnae3_dev_tqp_txrx_indep_supported(hdev) \

	test_bit(HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, (hdev)->ae_dev->caps)



#define hnae3_dev_hw_pad_supported(hdev) \

	test_bit(HNAE3_DEV_SUPPORT_HW_PAD_B, (hdev)->ae_dev->caps)



#define hnae3_dev_stash_supported(hdev) \

	test_bit(HNAE3_DEV_SUPPORT_STASH_B, (hdev)->ae_dev->caps)



#define ring_ptr_move_fw(ring, p) \

	((ring)->p = ((ring)->p + 1) % (ring)->desc_num)
@@ -209,6 +267,17 @@ struct hnae3_ring_chain_node { 
#define HNAE3_IS_TX_RING(node) \

	(((node)->flag & (1 << HNAE3_RING_TYPE_B)) == HNAE3_RING_TYPE_TX)



/* device specification info from firmware */

struct hnae3_dev_specs {

	u32 mac_entry_num; /* number of mac-vlan table entry */

	u32 mng_entry_num; /* number of manager table entry */

	u32 max_tm_rate;

	u16 rss_ind_tbl_size;

	u16 rss_key_size;

	u16 int_ql_max; /* max value of interrupt coalesce based on INT_QL */

	u8 max_non_tso_bd_num; /* max BD number of one non-TSO packet */

};



struct hnae3_client_ops {

	int (*init_instance)(struct hnae3_handle *handle);

	void (*uninit_instance)(struct hnae3_handle *handle, bool reset);
@@ -229,12 +298,16 @@ struct hnae3_client { 
	struct list_head node;

};



#define HNAE3_DEV_CAPS_MAX_NUM	96

struct hnae3_ae_dev {

	struct pci_dev *pdev;

	const struct hnae3_ae_ops *ops;

	struct list_head node;

	u32 flag;

	unsigned long hw_err_reset_req;

	struct hnae3_dev_specs dev_specs;

	u32 dev_version;

	unsigned long caps[BITS_TO_LONGS(HNAE3_DEV_CAPS_MAX_NUM)];

	void *priv;

};

drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c

+24 −0
Original line number Diff line number Diff line
@@ -244,6 +244,7 @@ static void hns3_dbg_help(struct hnae3_handle *h) 
	dev_info(&h->pdev->dev, "queue info <number>\n");

	dev_info(&h->pdev->dev, "queue map\n");

	dev_info(&h->pdev->dev, "bd info <q_num> <bd index>\n");

	dev_info(&h->pdev->dev, "dev capability\n");



	if (!hns3_is_phys_func(h->pdev))

		return;
@@ -285,6 +286,27 @@ static void hns3_dbg_help(struct hnae3_handle *h) 
	dev_info(&h->pdev->dev, "%s", printf_buf);

}



static void hns3_dbg_dev_caps(struct hnae3_handle *h)

{

	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev);

	unsigned long *caps;



	caps = ae_dev->caps;



	dev_info(&h->pdev->dev, "support FD: %s\n",

		 test_bit(HNAE3_DEV_SUPPORT_FD_B, caps) ? "yes" : "no");

	dev_info(&h->pdev->dev, "support GRO: %s\n",

		 test_bit(HNAE3_DEV_SUPPORT_GRO_B, caps) ? "yes" : "no");

	dev_info(&h->pdev->dev, "support FEC: %s\n",

		 test_bit(HNAE3_DEV_SUPPORT_FEC_B, caps) ? "yes" : "no");

	dev_info(&h->pdev->dev, "support UDP GSO: %s\n",

		 test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, caps) ? "yes" : "no");

	dev_info(&h->pdev->dev, "support PTP: %s\n",

		 test_bit(HNAE3_DEV_SUPPORT_PTP_B, caps) ? "yes" : "no");

	dev_info(&h->pdev->dev, "support INT QL: %s\n",

		 test_bit(HNAE3_DEV_SUPPORT_INT_QL_B, caps) ? "yes" : "no");

}



static ssize_t hns3_dbg_cmd_read(struct file *filp, char __user *buffer,

				 size_t count, loff_t *ppos)

{
@@ -360,6 +382,8 @@ static ssize_t hns3_dbg_cmd_write(struct file *filp, const char __user *buffer, 
		ret = hns3_dbg_queue_map(handle);

	else if (strncmp(cmd_buf, "bd info", 7) == 0)

		ret = hns3_dbg_bd_info(handle, cmd_buf);

	else if (strncmp(cmd_buf, "dev capability", 14) == 0)

		hns3_dbg_dev_caps(handle);

	else if (handle->ae_algo->ops->dbg_run_cmd)

		ret = handle->ae_algo->ops->dbg_run_cmd(handle, cmd_buf);

	else

drivers/net/ethernet/hisilicon/hns3/hns3_enet.c

+7 −13
Original line number Diff line number Diff line
@@ -629,9 +629,11 @@ void hns3_enable_vlan_filter(struct net_device *netdev, bool enable) 
{

	struct hns3_nic_priv *priv = netdev_priv(netdev);

	struct hnae3_handle *h = priv->ae_handle;

	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev);

	bool last_state;



	if (h->pdev->revision >= 0x21 && h->ae_algo->ops->enable_vlan_filter) {

	if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2 &&

	    h->ae_algo->ops->enable_vlan_filter) {

		last_state = h->netdev_flags & HNAE3_VLAN_FLTR ? true : false;

		if (enable != last_state) {

			netdev_info(netdev,
@@ -2074,15 +2076,6 @@ static void hns3_disable_sriov(struct pci_dev *pdev) 
	pci_disable_sriov(pdev);

}



static void hns3_get_dev_capability(struct pci_dev *pdev,

				    struct hnae3_ae_dev *ae_dev)

{

	if (pdev->revision >= 0x21) {

		hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_FD_B, 1);

		hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_GRO_B, 1);

	}

}



/* hns3_probe - Device initialization routine

 * @pdev: PCI device information struct

 * @ent: entry in hns3_pci_tbl
@@ -2104,7 +2097,6 @@ static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 


	ae_dev->pdev = pdev;

	ae_dev->flag = ent->driver_data;

	hns3_get_dev_capability(pdev, ae_dev);

	pci_set_drvdata(pdev, ae_dev);



	ret = hnae3_register_ae_dev(ae_dev);
@@ -2265,6 +2257,7 @@ static void hns3_set_default_feature(struct net_device *netdev) 
{

	struct hnae3_handle *h = hns3_get_handle(netdev);

	struct pci_dev *pdev = h->pdev;

	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);



	netdev->priv_flags |= IFF_UNICAST_FLT;
@@ -2302,7 +2295,7 @@ static void hns3_set_default_feature(struct net_device *netdev) 
		NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC |

		NETIF_F_FRAGLIST;



	if (pdev->revision >= 0x21) {

	if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {

		netdev->hw_features |= NETIF_F_GRO_HW;

		netdev->features |= NETIF_F_GRO_HW;
@@ -2801,8 +2794,9 @@ static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring, 
{

	struct hnae3_handle *handle = ring->tqp->handle;

	struct pci_dev *pdev = ring->tqp->handle->pdev;

	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);



	if (pdev->revision == 0x20) {

	if (unlikely(ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)) {

		*vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);

		if (!(*vlan_tag & VLAN_VID_MASK))

			*vlan_tag = le16_to_cpu(desc->rx.vlan_tag);

drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c

+19 −11
Original line number Diff line number Diff line
@@ -77,6 +77,7 @@ static const struct hns3_stats hns3_rxq_stats[] = { 
static int hns3_lp_setup(struct net_device *ndev, enum hnae3_loop loop, bool en)

{

	struct hnae3_handle *h = hns3_get_handle(ndev);

	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev);

	bool vlan_filter_enable;

	int ret;
@@ -96,7 +97,7 @@ static int hns3_lp_setup(struct net_device *ndev, enum hnae3_loop loop, bool en) 
		break;

	}



	if (ret || h->pdev->revision >= 0x21)

	if (ret || ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2)

		return ret;



	if (en) {
@@ -147,6 +148,7 @@ static void hns3_lp_setup_skb(struct sk_buff *skb) 


	struct net_device *ndev = skb->dev;

	struct hnae3_handle *handle;

	struct hnae3_ae_dev *ae_dev;

	unsigned char *packet;

	struct ethhdr *ethh;

	unsigned int i;
@@ -163,7 +165,8 @@ static void hns3_lp_setup_skb(struct sk_buff *skb) 
	 * the purpose of mac or serdes selftest.

	 */

	handle = hns3_get_handle(ndev);

	if (handle->pdev->revision == 0x20)

	ae_dev = pci_get_drvdata(handle->pdev);

	if (ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)

		ethh->h_dest[5] += HNS3_NIC_LB_DST_MAC_ADDR;

	eth_zero_addr(ethh->h_source);

	ethh->h_proto = htons(ETH_P_ARP);
@@ -761,6 +764,7 @@ static int hns3_set_link_ksettings(struct net_device *netdev, 
				   const struct ethtool_link_ksettings *cmd)

{

	struct hnae3_handle *handle = hns3_get_handle(netdev);

	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);

	const struct hnae3_ae_ops *ops = handle->ae_algo->ops;

	int ret;
@@ -782,7 +786,7 @@ static int hns3_set_link_ksettings(struct net_device *netdev, 
		return phy_ethtool_ksettings_set(netdev->phydev, cmd);

	}



	if (handle->pdev->revision == 0x20)

	if (ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)

		return -EOPNOTSUPP;



	ret = hns3_check_ksettings_param(netdev, cmd);
@@ -846,11 +850,12 @@ static int hns3_set_rss(struct net_device *netdev, const u32 *indir, 
			const u8 *key, const u8 hfunc)

{

	struct hnae3_handle *h = hns3_get_handle(netdev);

	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev);



	if (!h->ae_algo->ops->set_rss)

		return -EOPNOTSUPP;



	if ((h->pdev->revision == 0x20 &&

	if ((ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2 &&

	     hfunc != ETH_RSS_HASH_TOP) || (hfunc != ETH_RSS_HASH_NO_CHANGE &&

	     hfunc != ETH_RSS_HASH_TOP && hfunc != ETH_RSS_HASH_XOR)) {

		netdev_err(netdev, "hash func not supported\n");
@@ -1071,9 +1076,6 @@ static int hns3_nway_reset(struct net_device *netdev) 
	if (phy)

		return genphy_restart_aneg(phy);



	if (handle->pdev->revision == 0x20)

		return -EOPNOTSUPP;



	return ops->restart_autoneg(handle);

}
@@ -1361,11 +1363,12 @@ static int hns3_get_fecparam(struct net_device *netdev, 
			     struct ethtool_fecparam *fec)

{

	struct hnae3_handle *handle = hns3_get_handle(netdev);

	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);

	const struct hnae3_ae_ops *ops = handle->ae_algo->ops;

	u8 fec_ability;

	u8 fec_mode;



	if (handle->pdev->revision == 0x20)

	if (!test_bit(HNAE3_DEV_SUPPORT_FEC_B, ae_dev->caps))

		return -EOPNOTSUPP;



	if (!ops->get_fec)
@@ -1383,10 +1386,11 @@ static int hns3_set_fecparam(struct net_device *netdev, 
			     struct ethtool_fecparam *fec)

{

	struct hnae3_handle *handle = hns3_get_handle(netdev);

	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);

	const struct hnae3_ae_ops *ops = handle->ae_algo->ops;

	u32 fec_mode;



	if (handle->pdev->revision == 0x20)

	if (!test_bit(HNAE3_DEV_SUPPORT_FEC_B, ae_dev->caps))

		return -EOPNOTSUPP;



	if (!ops->set_fec)
@@ -1404,11 +1408,13 @@ static int hns3_get_module_info(struct net_device *netdev, 
#define HNS3_SFF_8636_V1_3 0x03



	struct hnae3_handle *handle = hns3_get_handle(netdev);

	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);

	const struct hnae3_ae_ops *ops = handle->ae_algo->ops;

	struct hns3_sfp_type sfp_type;

	int ret;



	if (handle->pdev->revision == 0x20 || !ops->get_module_eeprom)

	if (ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2 ||

	    !ops->get_module_eeprom)

		return -EOPNOTSUPP;



	memset(&sfp_type, 0, sizeof(sfp_type));
@@ -1452,9 +1458,11 @@ static int hns3_get_module_eeprom(struct net_device *netdev, 
				  struct ethtool_eeprom *ee, u8 *data)

{

	struct hnae3_handle *handle = hns3_get_handle(netdev);

	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);

	const struct hnae3_ae_ops *ops = handle->ae_algo->ops;



	if (handle->pdev->revision == 0x20 || !ops->get_module_eeprom)

	if (ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2 ||

	    !ops->get_module_eeprom)

		return -EOPNOTSUPP;



	if (!ee->len)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c

+52 −13
Original line number Diff line number Diff line
@@ -330,9 +330,37 @@ int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num) 
	return retval;

}



static enum hclge_cmd_status hclge_cmd_query_firmware_version(

		struct hclge_hw *hw, u32 *version)

static void hclge_set_default_capability(struct hclge_dev *hdev)

{

	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);



	set_bit(HNAE3_DEV_SUPPORT_FD_B, ae_dev->caps);

	set_bit(HNAE3_DEV_SUPPORT_GRO_B, ae_dev->caps);

	set_bit(HNAE3_DEV_SUPPORT_FEC_B, ae_dev->caps);

}



static void hclge_parse_capability(struct hclge_dev *hdev,

				   struct hclge_query_version_cmd *cmd)

{

	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);

	u32 caps;



	caps = __le32_to_cpu(cmd->caps[0]);



	if (hnae3_get_bit(caps, HCLGE_CAP_UDP_GSO_B))

		set_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, ae_dev->caps);

	if (hnae3_get_bit(caps, HCLGE_CAP_PTP_B))

		set_bit(HNAE3_DEV_SUPPORT_PTP_B, ae_dev->caps);

	if (hnae3_get_bit(caps, HCLGE_CAP_INT_QL_B))

		set_bit(HNAE3_DEV_SUPPORT_INT_QL_B, ae_dev->caps);

	if (hnae3_get_bit(caps, HCLGE_CAP_TQP_TXRX_INDEP_B))

		set_bit(HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, ae_dev->caps);

}



static enum hclge_cmd_status

hclge_cmd_query_version_and_capability(struct hclge_dev *hdev)

{

	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);

	struct hclge_query_version_cmd *resp;

	struct hclge_desc desc;

	int ret;
@@ -340,9 +368,20 @@ static enum hclge_cmd_status hclge_cmd_query_firmware_version( 
	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FW_VER, 1);

	resp = (struct hclge_query_version_cmd *)desc.data;



	ret = hclge_cmd_send(hw, &desc, 1);

	if (!ret)

		*version = le32_to_cpu(resp->firmware);

	ret = hclge_cmd_send(&hdev->hw, &desc, 1);

	if (ret)

		return ret;



	hdev->fw_version = le32_to_cpu(resp->firmware);



	ae_dev->dev_version = le32_to_cpu(resp->hardware) <<

					 HNAE3_PCI_REVISION_BIT_SIZE;

	ae_dev->dev_version |= hdev->pdev->revision;



	if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2)

		hclge_set_default_capability(hdev);



	hclge_parse_capability(hdev, resp);



	return ret;

}
@@ -402,7 +441,6 @@ static int hclge_firmware_compat_config(struct hclge_dev *hdev) 


int hclge_cmd_init(struct hclge_dev *hdev)

{

	u32 version;

	int ret;



	spin_lock_bh(&hdev->hw.cmq.csq.lock);
@@ -431,22 +469,23 @@ int hclge_cmd_init(struct hclge_dev *hdev) 
		goto err_cmd_init;

	}



	ret = hclge_cmd_query_firmware_version(&hdev->hw, &version);

	/* get version and device capabilities */

	ret = hclge_cmd_query_version_and_capability(hdev);

	if (ret) {

		dev_err(&hdev->pdev->dev,

			"firmware version query failed %d\n", ret);

			"failed to query version and capabilities, ret = %d\n",

			ret);

		goto err_cmd_init;

	}

	hdev->fw_version = version;



	dev_info(&hdev->pdev->dev, "The firmware version is %lu.%lu.%lu.%lu\n",

		 hnae3_get_field(version, HNAE3_FW_VERSION_BYTE3_MASK,

		 hnae3_get_field(hdev->fw_version, HNAE3_FW_VERSION_BYTE3_MASK,

				 HNAE3_FW_VERSION_BYTE3_SHIFT),

		 hnae3_get_field(version, HNAE3_FW_VERSION_BYTE2_MASK,

		 hnae3_get_field(hdev->fw_version, HNAE3_FW_VERSION_BYTE2_MASK,

				 HNAE3_FW_VERSION_BYTE2_SHIFT),

		 hnae3_get_field(version, HNAE3_FW_VERSION_BYTE1_MASK,

		 hnae3_get_field(hdev->fw_version, HNAE3_FW_VERSION_BYTE1_MASK,

				 HNAE3_FW_VERSION_BYTE1_SHIFT),

		 hnae3_get_field(version, HNAE3_FW_VERSION_BYTE0_MASK,

		 hnae3_get_field(hdev->fw_version, HNAE3_FW_VERSION_BYTE0_MASK,

				 HNAE3_FW_VERSION_BYTE0_SHIFT));



	/* ask the firmware to enable some features, driver can work without