Commit 601e5d46 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'riscv-jh7110-clk-reset-for-6.4' of... 

Merge tag 'riscv-jh7110-clk-reset-for-6.4' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux

 into clk-starfive

Pull Starfive clk driver updates from Conor Dooley:

 - Initial JH7110 clk/reset support

A rake of patches, initially worked on by Emil & later picked up by Hal
that add support for the sys/aon clock & reset controllers on StarFive's
JH7110 SoC.

This SoC is largely similar to the existing JH7100, so a bunch of
refactoring is done to share as many bits as possible between the two.
What's here (plus the already applied pinctrl bits) should be sufficient
to boot a basic initramfs.

Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>

* tag 'riscv-jh7110-clk-reset-for-6.4' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
  MAINTAINERS: generalise StarFive clk/reset entries
  reset: starfive: Add StarFive JH7110 reset driver
  clk: starfive: Add StarFive JH7110 always-on clock driver
  clk: starfive: Add StarFive JH7110 system clock driver
  reset: starfive: jh71x0: Use 32bit I/O on 32bit registers
  reset: starfive: Rename "jh7100" to "jh71x0" for the common code
  reset: starfive: Extract the common JH71X0 reset code
  reset: starfive: Factor out common JH71X0 reset code
  reset: Create subdirectory for StarFive drivers
  reset: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE
  clk: starfive: Rename "jh7100" to "jh71x0" for the common code
  clk: starfive: Rename clk-starfive-jh7100.h to clk-starfive-jh71x0.h
  clk: starfive: Factor out common JH7100 and JH7110 code
  clk: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE
  dt-bindings: clock: Add StarFive JH7110 always-on clock and reset generator
  dt-bindings: clock: Add StarFive JH7110 system clock and reset generator
parents eeac8ede 63a30e1f

Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/starfive,jh7110-aoncrg.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: StarFive JH7110 Always-On Clock and Reset Generator



maintainers:

  - Emil Renner Berthing <kernel@esmil.dk>



properties:

  compatible:

    const: starfive,jh7110-aoncrg



  reg:

    maxItems: 1



  clocks:

    oneOf:

      - items:

          - description: Main Oscillator (24 MHz)

          - description: GMAC0 RMII reference or GMAC0 RGMII RX

          - description: STG AXI/AHB

          - description: APB Bus

          - description: GMAC0 GTX



      - items:

          - description: Main Oscillator (24 MHz)

          - description: GMAC0 RMII reference or GMAC0 RGMII RX

          - description: STG AXI/AHB or GMAC0 RGMII RX

          - description: APB Bus or STG AXI/AHB

          - description: GMAC0 GTX or APB Bus

          - description: RTC Oscillator (32.768 kHz) or GMAC0 GTX



      - items:

          - description: Main Oscillator (24 MHz)

          - description: GMAC0 RMII reference

          - description: GMAC0 RGMII RX

          - description: STG AXI/AHB

          - description: APB Bus

          - description: GMAC0 GTX

          - description: RTC Oscillator (32.768 kHz)



  clock-names:

    oneOf:

      - minItems: 5

        items:

          - const: osc

          - enum:

              - gmac0_rmii_refin

              - gmac0_rgmii_rxin

          - const: stg_axiahb

          - const: apb_bus

          - const: gmac0_gtxclk

          - const: rtc_osc



      - minItems: 6

        items:

          - const: osc

          - const: gmac0_rmii_refin

          - const: gmac0_rgmii_rxin

          - const: stg_axiahb

          - const: apb_bus

          - const: gmac0_gtxclk

          - const: rtc_osc



  '#clock-cells':

    const: 1

    description:

      See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.



  '#reset-cells':

    const: 1

    description:

      See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - '#clock-cells'

  - '#reset-cells'



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/starfive,jh7110-crg.h>



    clock-controller@17000000 {

        compatible = "starfive,jh7110-aoncrg";

        reg = <0x17000000 0x10000>;

        clocks = <&osc>, <&gmac0_rmii_refin>,

                 <&gmac0_rgmii_rxin>,

                 <&syscrg JH7110_SYSCLK_STG_AXIAHB>,

                 <&syscrg JH7110_SYSCLK_APB_BUS>,

                 <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>,

                 <&rtc_osc>;

        clock-names = "osc", "gmac0_rmii_refin",

                      "gmac0_rgmii_rxin", "stg_axiahb",

                      "apb_bus", "gmac0_gtxclk",

                      "rtc_osc";

        #clock-cells = <1>;

        #reset-cells = <1>;

    };

Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/starfive,jh7110-syscrg.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: StarFive JH7110 System Clock and Reset Generator



maintainers:

  - Emil Renner Berthing <kernel@esmil.dk>



properties:

  compatible:

    const: starfive,jh7110-syscrg



  reg:

    maxItems: 1



  clocks:

    oneOf:

      - items:

          - description: Main Oscillator (24 MHz)

          - description: GMAC1 RMII reference or GMAC1 RGMII RX

          - description: External I2S TX bit clock

          - description: External I2S TX left/right channel clock

          - description: External I2S RX bit clock

          - description: External I2S RX left/right channel clock

          - description: External TDM clock

          - description: External audio master clock



      - items:

          - description: Main Oscillator (24 MHz)

          - description: GMAC1 RMII reference

          - description: GMAC1 RGMII RX

          - description: External I2S TX bit clock

          - description: External I2S TX left/right channel clock

          - description: External I2S RX bit clock

          - description: External I2S RX left/right channel clock

          - description: External TDM clock

          - description: External audio master clock



  clock-names:

    oneOf:

      - items:

          - const: osc

          - enum:

              - gmac1_rmii_refin

              - gmac1_rgmii_rxin

          - const: i2stx_bclk_ext

          - const: i2stx_lrck_ext

          - const: i2srx_bclk_ext

          - const: i2srx_lrck_ext

          - const: tdm_ext

          - const: mclk_ext



      - items:

          - const: osc

          - const: gmac1_rmii_refin

          - const: gmac1_rgmii_rxin

          - const: i2stx_bclk_ext

          - const: i2stx_lrck_ext

          - const: i2srx_bclk_ext

          - const: i2srx_lrck_ext

          - const: tdm_ext

          - const: mclk_ext



  '#clock-cells':

    const: 1

    description:

      See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.



  '#reset-cells':

    const: 1

    description:

      See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - '#clock-cells'

  - '#reset-cells'



additionalProperties: false



examples:

  - |

    clock-controller@13020000 {

        compatible = "starfive,jh7110-syscrg";

        reg = <0x13020000 0x10000>;

        clocks = <&osc>, <&gmac1_rmii_refin>,

                 <&gmac1_rgmii_rxin>,

                 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,

                 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,

                 <&tdm_ext>, <&mclk_ext>;

        clock-names = "osc", "gmac1_rmii_refin",

                      "gmac1_rgmii_rxin",

                      "i2stx_bclk_ext", "i2stx_lrck_ext",

                      "i2srx_bclk_ext", "i2srx_lrck_ext",

                      "tdm_ext", "mclk_ext";

        #clock-cells = <1>;

        #reset-cells = <1>;

    };

MAINTAINERS

+12 −10
Original line number Diff line number Diff line
@@ -19907,19 +19907,20 @@ M: Emil Renner Berthing <kernel@esmil.dk> 
S:	Maintained

F:	arch/riscv/boot/dts/starfive/









STARFIVE JH7100 CLOCK DRIVERS









M:	Emil Renner Berthing <kernel@esmil.dk>









S:	Maintained









F:	Documentation/devicetree/bindings/clock/starfive,jh7100-*.yaml









F:	drivers/clk/starfive/clk-starfive-jh7100*









F:	include/dt-bindings/clock/starfive-jh7100*.h

















STARFIVE JH7110 MMC/SD/SDIO DRIVER









M:	William Qiu <william.qiu@starfivetech.com>









S:	Supported









F:	Documentation/devicetree/bindings/mmc/starfive*









F:	drivers/mmc/host/dw_mmc-starfive.c

















STARFIVE JH71X0 CLOCK DRIVERS









M:	Emil Renner Berthing <kernel@esmil.dk>









M:	Hal Feng <hal.feng@starfivetech.com>









S:	Maintained









F:	Documentation/devicetree/bindings/clock/starfive,jh71*.yaml









F:	drivers/clk/starfive/clk-starfive-jh71*









F:	include/dt-bindings/clock/starfive?jh71*.h

















STARFIVE JH71X0 PINCTRL DRIVERS









M:	Emil Renner Berthing <kernel@esmil.dk>









M:	Jianlong Huang <jianlong.huang@starfivetech.com>








@@ -19930,12 +19931,13 @@ F:	drivers/pinctrl/starfive/pinctrl-starfive-jh71*







F:	include/dt-bindings/pinctrl/pinctrl-starfive-jh7100.h









F:	include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h

















STARFIVE JH7100 RESET CONTROLLER DRIVER









STARFIVE JH71X0 RESET CONTROLLER DRIVERS









M:	Emil Renner Berthing <kernel@esmil.dk>









M:	Hal Feng <hal.feng@starfivetech.com>









S:	Maintained









F:	Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml









F:	drivers/reset/reset-starfive-jh7100.c









F:	include/dt-bindings/reset/starfive-jh7100.h









F:	drivers/reset/starfive/reset-starfive-jh71*









F:	include/dt-bindings/reset/starfive?jh71*.h

















STARFIVE JH71XX PMU CONTROLLER DRIVER









M:	Walker Chen <walker.chen@starfivetech.com>

























drivers/clk/Makefile



+1
−1






























Original line number
Diff line number
Diff line







@@ -117,7 +117,7 @@ obj-$(CONFIG_PLAT_SPEAR)		+= spear/







obj-y					+= sprd/









obj-$(CONFIG_ARCH_STI)			+= st/









obj-$(CONFIG_ARCH_STM32)		+= stm32/









obj-$(CONFIG_SOC_STARFIVE)		+= starfive/









obj-y					+= starfive/









obj-$(CONFIG_ARCH_SUNXI)		+= sunxi/









obj-y					+= sunxi-ng/









obj-$(CONFIG_ARCH_TEGRA)		+= tegra/
































drivers/clk/starfive/Kconfig



+30
−3






























Original line number
Diff line number
Diff line









# SPDX-License-Identifier: GPL-2.0



















config CLK_STARFIVE_JH71X0









	bool



















config CLK_STARFIVE_JH7100









	bool "StarFive JH7100 clock support"









	depends on SOC_STARFIVE || COMPILE_TEST









	default SOC_STARFIVE









	depends on ARCH_STARFIVE || COMPILE_TEST









	select CLK_STARFIVE_JH71X0









	default ARCH_STARFIVE









	help









	  Say yes here to support the clock controller on the StarFive JH7100









	  SoC.








@@ -11,7 +15,30 @@ config CLK_STARFIVE_JH7100







config CLK_STARFIVE_JH7100_AUDIO









	tristate "StarFive JH7100 audio clock support"









	depends on CLK_STARFIVE_JH7100









	default m if SOC_STARFIVE









	select CLK_STARFIVE_JH71X0









	default m if ARCH_STARFIVE









	help









	  Say Y or M here to support the audio clocks on the StarFive JH7100









	  SoC.



















config CLK_STARFIVE_JH7110_SYS









	bool "StarFive JH7110 system clock support"









	depends on ARCH_STARFIVE || COMPILE_TEST









	select AUXILIARY_BUS









	select CLK_STARFIVE_JH71X0









	select RESET_STARFIVE_JH7110









	default ARCH_STARFIVE









	help









	  Say yes here to support the system clock controller on the









	  StarFive JH7110 SoC.



















config CLK_STARFIVE_JH7110_AON









	tristate "StarFive JH7110 always-on clock support"









	depends on CLK_STARFIVE_JH7110_SYS









	select AUXILIARY_BUS









	select CLK_STARFIVE_JH71X0









	select RESET_STARFIVE_JH7110









	default m if ARCH_STARFIVE









	help









	  Say yes here to support the always-on clock controller on the









	  StarFive JH7110 SoC.