Commit 60191843 authored by Biju Das's avatar Biju Das Committed by Geert Uytterhoeven
Browse files

clk: renesas: r9a07g044: Add M1 clock support 



Add support for M1 clock which is sourced from FOUTPOSTDIV.

Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220430114156.6260-5-biju.das.jz@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 46bb3e15

drivers/clk/renesas/r9a07g044-cpg.c

+10 −1
Original line number Diff line number Diff line
@@ -40,6 +40,8 @@ enum clk_ids { 
	CLK_DIV_PLL3_C,

	CLK_PLL4,

	CLK_PLL5,

	CLK_PLL5_FOUTPOSTDIV,

	CLK_PLL5_FOUT1PH0,

	CLK_PLL5_FOUT3,

	CLK_PLL5_250,

	CLK_PLL6,
@@ -52,6 +54,7 @@ enum clk_ids { 
	CLK_SD0_DIV4,

	CLK_SD1_DIV4,

	CLK_SEL_GPU2,

	CLK_SEL_PLL5_4,



	/* Module Clocks */

	MOD_CLK_BASE,
@@ -77,12 +80,13 @@ static const struct clk_div_table dtable_1_32[] = { 


/* Mux clock tables */

static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" };

static const char * const sel_pll5_4[] = { ".pll5_foutpostdiv", ".pll5_fout1ph0" };

static const char * const sel_pll6_2[]	= { ".pll6_250", ".pll5_250" };

static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" };

static const char * const sel_gpu2[] = { ".pll6", ".pll3_div2_2" };



static const struct {

	struct cpg_core_clk common[44];

	struct cpg_core_clk common[48];

#ifdef CONFIG_CLK_R9A07G054

	struct cpg_core_clk drp[0];

#endif
@@ -127,6 +131,10 @@ static const struct { 
		DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2),

		DEF_MUX(".sel_gpu2", CLK_SEL_GPU2, SEL_GPU2,

			sel_gpu2, ARRAY_SIZE(sel_gpu2), 0, CLK_MUX_READ_ONLY),

		DEF_PLL5_FOUTPOSTDIV(".pll5_foutpostdiv", CLK_PLL5_FOUTPOSTDIV, CLK_EXTAL),

		DEF_FIXED(".pll5_fout1ph0", CLK_PLL5_FOUT1PH0, CLK_PLL5_FOUTPOSTDIV, 1, 2),

		DEF_PLL5_4_MUX(".sel_pll5_4", CLK_SEL_PLL5_4, SEL_PLL5_4,

			       sel_pll5_4, ARRAY_SIZE(sel_pll5_4)),



		/* Core output clk */

		DEF_DIV("I", R9A07G044_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8,
@@ -154,6 +162,7 @@ static const struct { 
		DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G044_CLK_SD1, 1, 4),

		DEF_DIV("G", R9A07G044_CLK_G, CLK_SEL_GPU2, DIVGPU, dtable_1_8,

			CLK_DIVIDER_HIWORD_MASK),

		DEF_FIXED("M1", R9A07G044_CLK_M1, CLK_PLL5_FOUTPOSTDIV, 1, 1),

	},

#ifdef CONFIG_CLK_R9A07G054

	.drp = {