Unverified Commit 5ffabf50 authored by Maxime Ripard's avatar Maxime Ripard
Browse files

drm/vc4: crtc: Turn pixelvalve reset into a function 



The driver resets the pixelvalve FIFO in a number of occurences without
always using the same sequence.

Since this will be critical for BCM2711, let's move that sequence to a
function so that we are consistent.

Signed-off-by: default avatarMaxime Ripard <maxime@cerno.tech>
Tested-by: default avatarChanwoo Choi <cw00.choi@samsung.com>
Tested-by: default avatarHoegeun Kwon <hoegeun.kwon@samsung.com>
Tested-by: default avatarStefan Wahren <stefan.wahren@i2se.com>
Reviewed-by: default avatarEric Anholt <eric@anholt.net>
Link: https://patchwork.freedesktop.org/patch/msgid/fb31003a9eee02c4b949556299ff41f0a113499a.1599120059.git-series.maxime@cerno.tech
parent eb92bc72

drivers/gpu/drm/vc4/vc4_crtc.c

+13 −7
Original line number Diff line number Diff line
@@ -267,6 +267,15 @@ static struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc) 
	return NULL;

}



static void vc4_crtc_pixelvalve_reset(struct drm_crtc *crtc)

{

	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);



	/* The PV needs to be disabled before it can be flushed */

	CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) & ~PV_CONTROL_EN);

	CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_FIFO_CLR);

}



static void vc4_crtc_config_pv(struct drm_crtc *crtc)

{

	struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc);
@@ -282,10 +291,7 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc) 
	u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;

	u8 ppc = pv_data->pixels_per_clock;



	/* Reset the PV fifo. */

	CRTC_WRITE(PV_CONTROL, 0);

	CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR | PV_CONTROL_EN);

	CRTC_WRITE(PV_CONTROL, 0);

	vc4_crtc_pixelvalve_reset(crtc);



	CRTC_WRITE(PV_HORZA,

		   VC4_SET_FIELD((mode->htotal - mode->hsync_end) * pixel_rep / ppc,
@@ -430,9 +436,9 @@ static void vc4_crtc_atomic_enable(struct drm_crtc *crtc, 


	require_hvs_enabled(dev);



	/* Reset the PV fifo. */

	CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) |

		   PV_CONTROL_FIFO_CLR | PV_CONTROL_EN);

	vc4_crtc_pixelvalve_reset(crtc);



	CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_EN);



	/* Enable vblank irq handling before crtc is started otherwise

	 * drm_crtc_get_vblank() fails in vc4_crtc_update_dlist().