Commit 5fe0faa6 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov
Browse files

drm/msm/dpu: use common helper for WB and SSPP QoS setup 



Rework SSPP and WB code to use common helper for programming QoS
settings.

Reviewed-by: default avatarJeykumar Sankaran <quic_jeykumar@quicinc.com>
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/537912/
Link: https://lore.kernel.org/r/20230518222238.3815293-10-dmitry.baryshkov@linaro.org


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
parent a5ebb27b

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c

+2 −2
Original line number Diff line number Diff line
@@ -102,7 +102,7 @@ static void dpu_encoder_phys_wb_set_qos_remap( 
static void dpu_encoder_phys_wb_set_qos(struct dpu_encoder_phys *phys_enc)

{

	struct dpu_hw_wb *hw_wb;

	struct dpu_hw_wb_qos_cfg qos_cfg;

	struct dpu_hw_qos_cfg qos_cfg;

	const struct dpu_mdss_cfg *catalog;

	const struct dpu_qos_lut_tbl *qos_lut_tb;
@@ -115,7 +115,7 @@ static void dpu_encoder_phys_wb_set_qos(struct dpu_encoder_phys *phys_enc) 


	hw_wb = phys_enc->hw_wb;



	memset(&qos_cfg, 0, sizeof(struct dpu_hw_wb_qos_cfg));

	memset(&qos_cfg, 0, sizeof(struct dpu_hw_qos_cfg));

	qos_cfg.danger_safe_en = true;

	qos_cfg.danger_lut =

		catalog->perf->danger_lut_tbl[DPU_QOS_LUT_USAGE_NRT];

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c

+7 −24
Original line number Diff line number Diff line
@@ -539,30 +539,15 @@ static void dpu_hw_sspp_setup_solidfill(struct dpu_sw_pipe *pipe, u32 color) 
				color);

}



static void dpu_hw_sspp_setup_danger_safe_lut(struct dpu_hw_sspp *ctx,

			u32 danger_lut,

			u32 safe_lut)

static void dpu_hw_sspp_setup_qos_lut(struct dpu_hw_sspp *ctx,

				      struct dpu_hw_qos_cfg *cfg)

{

	if (!ctx)

		return;



	DPU_REG_WRITE(&ctx->hw, SSPP_DANGER_LUT, danger_lut);

	DPU_REG_WRITE(&ctx->hw, SSPP_SAFE_LUT, safe_lut);

}



static void dpu_hw_sspp_setup_creq_lut(struct dpu_hw_sspp *ctx,

			u64 creq_lut)

{

	if (!ctx)

	if (!ctx || !cfg)

		return;



	if (ctx->cap && test_bit(DPU_SSPP_QOS_8LVL, &ctx->cap->features)) {

		DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT_0, creq_lut);

		DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT_1,

				creq_lut >> 32);

	} else {

		DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT, creq_lut);

	}

	_dpu_hw_setup_qos_lut(&ctx->hw, SSPP_DANGER_LUT,

			      test_bit(DPU_SSPP_QOS_8LVL, &ctx->cap->features),

			      cfg);

}



static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_sspp *ctx,
@@ -604,9 +589,7 @@ static void _setup_layer_ops(struct dpu_hw_sspp *c, 
	c->ops.setup_pe = dpu_hw_sspp_setup_pe_config;



	if (test_bit(DPU_SSPP_QOS, &features)) {

		c->ops.setup_danger_safe_lut =

			dpu_hw_sspp_setup_danger_safe_lut;

		c->ops.setup_creq_lut = dpu_hw_sspp_setup_creq_lut;

		c->ops.setup_qos_lut = dpu_hw_sspp_setup_qos_lut;

		c->ops.setup_qos_ctrl = dpu_hw_sspp_setup_qos_ctrl;

	}

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h

+4 −15
Original line number Diff line number Diff line
@@ -254,25 +254,14 @@ struct dpu_hw_sspp_ops { 
	void (*setup_sharpening)(struct dpu_hw_sspp *ctx,

			struct dpu_hw_sharp_cfg *cfg);



	/**

	 * setup_danger_safe_lut - setup danger safe LUTs

	 * @ctx: Pointer to pipe context

	 * @danger_lut: LUT for generate danger level based on fill level

	 * @safe_lut: LUT for generate safe level based on fill level

	 *

	 */

	void (*setup_danger_safe_lut)(struct dpu_hw_sspp *ctx,

			u32 danger_lut,

			u32 safe_lut);



	/**

	 * setup_creq_lut - setup CREQ LUT

	 * setup_qos_lut - setup QoS LUTs

	 * @ctx: Pointer to pipe context

	 * @creq_lut: LUT for generate creq level based on fill level

	 *

	 * @cfg: LUT configuration

	 */

	void (*setup_creq_lut)(struct dpu_hw_sspp *ctx,

			u64 creq_lut);

	void (*setup_qos_lut)(struct dpu_hw_sspp *ctx,

			struct dpu_hw_qos_cfg *cfg);



	/**

	 * setup_qos_ctrl - setup QoS control

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

+31 −0
Original line number Diff line number Diff line
@@ -73,6 +73,19 @@ static u32 dpu_hw_util_log_mask = DPU_DBG_MASK_NONE; 
#define QSEED3LITE_SEP_LUT_SIZE \

	        (QSEED3LITE_LUT_SIZE * QSEED3LITE_SEPARABLE_LUTS * sizeof(u32))



/* QOS_LUT */

#define QOS_DANGER_LUT                    0x00

#define QOS_SAFE_LUT                      0x04

#define QOS_CREQ_LUT                      0x08

#define QOS_QOS_CTRL                      0x0C

#define QOS_CREQ_LUT_0                    0x14

#define QOS_CREQ_LUT_1                    0x18



/* QOS_QOS_CTRL */

#define QOS_QOS_CTRL_DANGER_SAFE_EN       BIT(0)

#define QOS_QOS_CTRL_DANGER_VBLANK_MASK   GENMASK(5, 4)

#define QOS_QOS_CTRL_VBLANK_EN            BIT(16)

#define QOS_QOS_CTRL_CREQ_VBLANK_MASK     GENMASK(21, 20)



void dpu_reg_write(struct dpu_hw_blk_reg_map *c,

		u32 reg_off,
@@ -450,6 +463,24 @@ u64 _dpu_hw_get_qos_lut(const struct dpu_qos_lut_tbl *tbl, 
	return 0;

}



void _dpu_hw_setup_qos_lut(struct dpu_hw_blk_reg_map *c, u32 offset,

			   bool qos_8lvl,

			   const struct dpu_hw_qos_cfg *cfg)

{

	DPU_REG_WRITE(c, offset + QOS_DANGER_LUT, cfg->danger_lut);

	DPU_REG_WRITE(c, offset + QOS_SAFE_LUT, cfg->safe_lut);



	if (qos_8lvl) {

		DPU_REG_WRITE(c, offset + QOS_CREQ_LUT_0, cfg->creq_lut);

		DPU_REG_WRITE(c, offset + QOS_CREQ_LUT_1, cfg->creq_lut >> 32);

	} else {

		DPU_REG_WRITE(c, offset + QOS_CREQ_LUT, cfg->creq_lut);

	}



	DPU_REG_WRITE(c, offset + QOS_QOS_CTRL,

		      cfg->danger_safe_en ? QOS_QOS_CTRL_DANGER_SAFE_EN : 0);

}



void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c,

		u32 misr_ctrl_offset,

		bool enable, u32 frame_count)

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h

+21 −0
Original line number Diff line number Diff line
@@ -305,6 +305,23 @@ struct dpu_drm_scaler_v2 { 
	struct dpu_drm_de_v1 de;

};



/**

 * struct dpu_hw_qos_cfg: pipe QoS configuration

 * @danger_lut: LUT for generate danger level based on fill level

 * @safe_lut: LUT for generate safe level based on fill level

 * @creq_lut: LUT for generate creq level based on fill level

 * @creq_vblank: creq value generated to vbif during vertical blanking

 * @danger_vblank: danger value generated during vertical blanking

 * @vblank_en: enable creq_vblank and danger_vblank during vblank

 * @danger_safe_en: enable danger safe generation

 */

struct dpu_hw_qos_cfg {

	u32 danger_lut;

	u32 safe_lut;

	u64 creq_lut;

	bool danger_safe_en;

};



u32 *dpu_hw_util_get_log_mask_ptr(void);



void dpu_reg_write(struct dpu_hw_blk_reg_map *c,
@@ -336,6 +353,10 @@ void dpu_setup_cdp(struct dpu_hw_blk_reg_map *c, u32 offset, 
u64 _dpu_hw_get_qos_lut(const struct dpu_qos_lut_tbl *tbl,

		u32 total_fl);



void _dpu_hw_setup_qos_lut(struct dpu_hw_blk_reg_map *c, u32 offset,

			   bool qos_8lvl,

			   const struct dpu_hw_qos_cfg *cfg);



void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c,

		u32 misr_ctrl_offset,

		bool enable,