Commit 5fd974d1 authored by Daniele Ceraolo Spurio's avatar Daniele Ceraolo Spurio
Browse files

drm/i915/mtl: add initial definitions for GSC CS 



Starting on MTL, the GSC is no longer managed with direct MMIO access,
but we instead have a dedicated command streamer for it. As a first step
for adding support for this CS, add the required definitions.
Note that, although it is now a CS, the GSC retains its old
class:instance value (OTHER_CLASS instance 6)

Bspec: 65308, 45605
Signed-off-by: default avatarDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221102171047.2787951-2-daniele.ceraolospurio@intel.com
parent 178b8a36

drivers/gpu/drm/i915/gt/intel_engine_cs.c

+8 −0
Original line number Diff line number Diff line
@@ -244,6 +244,13 @@ static const struct engine_info intel_engines[] = { 
			{ .graphics_ver = 12, .base = GEN12_COMPUTE3_RING_BASE }

		}

	},

	[GSC0] = {

		.class = OTHER_CLASS,

		.instance = OTHER_GSC_INSTANCE,

		.mmio_bases = {

			{ .graphics_ver = 12, .base = MTL_GSC_RING_BASE }

		}

	},

};



/**
@@ -324,6 +331,7 @@ u32 intel_engine_context_size(struct intel_gt *gt, u8 class) 
	case VIDEO_DECODE_CLASS:

	case VIDEO_ENHANCEMENT_CLASS:

	case COPY_ENGINE_CLASS:

	case OTHER_CLASS:

		if (GRAPHICS_VER(gt->i915) < 8)

			return 0;

		return GEN8_LR_CONTEXT_OTHER_SIZE;

drivers/gpu/drm/i915/gt/intel_engine_types.h

+1 −0
Original line number Diff line number Diff line
@@ -136,6 +136,7 @@ enum intel_engine_id { 
	CCS2,

	CCS3,

#define _CCS(n) (CCS0 + (n))

	GSC0,

	I915_NUM_ENGINES

#define INVALID_ENGINE ((enum intel_engine_id)-1)

};

drivers/gpu/drm/i915/gt/intel_engine_user.c

+1 −0
Original line number Diff line number Diff line
@@ -140,6 +140,7 @@ const char *intel_engine_class_repr(u8 class) 
		[COPY_ENGINE_CLASS] = "bcs",

		[VIDEO_DECODE_CLASS] = "vcs",

		[VIDEO_ENHANCEMENT_CLASS] = "vecs",

		[OTHER_CLASS] = "other",

		[COMPUTE_CLASS] = "ccs",

	};

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -970,6 +970,7 @@ 
#define GEN11_VEBOX2_RING_BASE		0x1d8000

#define XEHP_VEBOX3_RING_BASE		0x1e8000

#define XEHP_VEBOX4_RING_BASE		0x1f8000

#define MTL_GSC_RING_BASE		0x11a000

#define GEN12_COMPUTE0_RING_BASE	0x1a000

#define GEN12_COMPUTE1_RING_BASE	0x1c000

#define GEN12_COMPUTE2_RING_BASE	0x1e000