Commit 5fd35f12 authored by Zhan Liu's avatar Zhan Liu Committed by Alex Deucher
Browse files

drm/amd/display: Enabling PSR on DCN30 on driver side 



[Why]
PSR needs to be enabled on DCN30. This is the driver part of PSR
enablement.

Also disabled retired DMCU on driver side, since DMCU is
not supported on DCN30 anymore.

[How]
Add necessary changes to enable PSR on DCN30.

Signed-off-by: default avatarZhan Liu <zhan.liu@amd.com>
Acked-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f9663cbd

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c

+16 −2
Original line number Diff line number Diff line
@@ -79,6 +79,7 @@ 


#include "reg_helper.h"

#include "dce/dmub_abm.h"

#include "dce/dmub_psr.h"

#include "dce/dce_aux.h"

#include "dce/dce_i2c.h"
@@ -832,7 +833,7 @@ static const struct dc_plane_cap plane_cap = { 
};



static const struct dc_debug_options debug_defaults_drv = {

	.disable_dmcu = true,

	.disable_dmcu = true, //No DMCU on DCN30

	.force_abm_enable = false,

	.timing_trace = false,

	.clock_trace = true,
@@ -849,10 +850,11 @@ static const struct dc_debug_options debug_defaults_drv = { 
	.underflow_assert_delay_us = 0xFFFFFFFF,

	.dwb_fi_phase = -1, // -1 = disable,

	.dmub_command_table = true,

	.disable_psr = false,

};



static const struct dc_debug_options debug_defaults_diags = {

	.disable_dmcu = true,

	.disable_dmcu = true, //No dmcu on DCN30

	.force_abm_enable = false,

	.timing_trace = true,

	.clock_trace = true,
@@ -865,6 +867,7 @@ static const struct dc_debug_options debug_defaults_diags = { 
	.scl_reset_length10 = true,

	.dwb_fi_phase = -1, // -1 = disable

	.dmub_command_table = true,

	.disable_psr = true,

	.enable_tri_buf = true,

};
@@ -1313,6 +1316,9 @@ static void dcn30_resource_destruct(struct dcn30_resource_pool *pool) 
			dce_abm_destroy(&pool->base.multiple_abms[i]);

	}



	if (pool->base.psr != NULL)

		dmub_psr_destroy(&pool->base.psr);



	if (pool->base.dccg != NULL)

		dcn_dccg_destroy(&pool->base.dccg);

}
@@ -2624,6 +2630,14 @@ static bool dcn30_resource_construct( 
		}

	}

	pool->base.timing_generator_count = i;

	/* PSR */

	pool->base.psr = dmub_psr_create(ctx);



	if (pool->base.psr == NULL) {

		dm_error("DC: failed to create PSR obj!\n");

		BREAK_TO_DEBUGGER();

		goto create_fail;

	}



	/* ABM */

	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {