Commit 5f8621c1 authored by Paolo Abeni's avatar Paolo Abeni
Browse files

Merge branch 'there-are-some-bugfix-for-the-hns3-ethernet-driver' 

Jijie Shao says:

====================
There are some bugfix for the HNS3 ethernet driver
====================

Link: https://lore.kernel.org/r/20230918074840.2650978-1-shaojijie@huawei.com


Signed-off-by: default avatarPaolo Abeni <pabeni@redhat.com>
parents 8070274b 07700630

drivers/net/ethernet/hisilicon/hns3/hns3_enet.c

+9 −0
Original line number Diff line number Diff line
@@ -3353,6 +3353,15 @@ static void hns3_set_default_feature(struct net_device *netdev) 
		  NETIF_F_HW_TC);



	netdev->hw_enc_features |= netdev->vlan_features | NETIF_F_TSO_MANGLEID;



	/* The device_version V3 hardware can't offload the checksum for IP in

	 * GRE packets, but can do it for NvGRE. So default to disable the

	 * checksum and GSO offload for GRE.

	 */

	if (ae_dev->dev_version > HNAE3_DEVICE_VERSION_V2) {

		netdev->features &= ~NETIF_F_GSO_GRE;

		netdev->features &= ~NETIF_F_GSO_GRE_CSUM;

	}

}



static int hns3_alloc_buffer(struct hns3_enet_ring *ring,

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

+12 −1
Original line number Diff line number Diff line
@@ -3564,9 +3564,14 @@ static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval) 
static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type,

				    u32 regclr)

{

#define HCLGE_IMP_RESET_DELAY		5



	switch (event_type) {

	case HCLGE_VECTOR0_EVENT_PTP:

	case HCLGE_VECTOR0_EVENT_RST:

		if (regclr == BIT(HCLGE_VECTOR0_IMPRESET_INT_B))

			mdelay(HCLGE_IMP_RESET_DELAY);



		hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr);

		break;

	case HCLGE_VECTOR0_EVENT_MBX:
@@ -7348,6 +7353,12 @@ static int hclge_del_cls_flower(struct hnae3_handle *handle, 
	ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, rule->location,

				   NULL, false);

	if (ret) {

		/* if tcam config fail, set rule state to TO_DEL,

		 * so the rule will be deleted when periodic

		 * task being scheduled.

		 */

		hclge_update_fd_list(hdev, HCLGE_FD_TO_DEL, rule->location, NULL);

		set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state);

		spin_unlock_bh(&hdev->fd_rule_lock);

		return ret;

	}
@@ -8824,7 +8835,7 @@ static void hclge_update_overflow_flags(struct hclge_vport *vport, 
	if (mac_type == HCLGE_MAC_ADDR_UC) {

		if (is_all_added)

			vport->overflow_promisc_flags &= ~HNAE3_OVERFLOW_UPE;

		else

		else if (hclge_is_umv_space_full(vport, true))

			vport->overflow_promisc_flags |= HNAE3_OVERFLOW_UPE;

	} else {

		if (is_all_added)

drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c

+2 −1
Original line number Diff line number Diff line
@@ -1855,7 +1855,8 @@ static void hclgevf_periodic_service_task(struct hclgevf_dev *hdev) 
	unsigned long delta = round_jiffies_relative(HZ);

	struct hnae3_handle *handle = &hdev->nic;



	if (test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state))

	if (test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state) ||

	    test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state))

		return;



	if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) {