Loading drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +2 −1 Original line number Diff line number Diff line Loading @@ -519,6 +519,7 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true, &duplicates); if (unlikely(r != 0)) { if (r != -ERESTARTSYS) DRM_ERROR("ttm_eu_reserve_buffers failed.\n"); goto error_free_pages; } Loading drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +4 −5 Original line number Diff line number Diff line Loading @@ -1959,6 +1959,7 @@ int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon) /* evict remaining vram memory */ amdgpu_bo_evict_vram(adev); amdgpu_atombios_scratch_regs_save(adev); pci_save_state(dev->pdev); if (suspend) { /* Shut down the device */ Loading Loading @@ -2010,6 +2011,7 @@ int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon) return r; } } amdgpu_atombios_scratch_regs_restore(adev); /* post card */ if (!amdgpu_card_posted(adev) || !resume) { Loading Loading @@ -2268,8 +2270,6 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev) } if (need_full_reset) { /* save scratch */ amdgpu_atombios_scratch_regs_save(adev); r = amdgpu_suspend(adev); retry: Loading @@ -2279,8 +2279,9 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev) amdgpu_display_stop_mc_access(adev, &save); amdgpu_wait_for_idle(adev, AMD_IP_BLOCK_TYPE_GMC); } amdgpu_atombios_scratch_regs_save(adev); r = amdgpu_asic_reset(adev); amdgpu_atombios_scratch_regs_restore(adev); /* post card */ amdgpu_atom_asic_init(adev->mode_info.atom_context); Loading @@ -2288,8 +2289,6 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev) dev_info(adev->dev, "GPU reset succeeded, trying to resume\n"); r = amdgpu_resume(adev); } /* restore scratch */ amdgpu_atombios_scratch_regs_restore(adev); } if (!r) { amdgpu_irq_gpu_reset_resume_helper(adev); Loading drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +1 −0 Original line number Diff line number Diff line Loading @@ -68,6 +68,7 @@ int amdgpu_fence_slab_init(void) void amdgpu_fence_slab_fini(void) { rcu_barrier(); kmem_cache_destroy(amdgpu_fence_slab); } /* Loading drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c +2 −0 Original line number Diff line number Diff line Loading @@ -239,6 +239,7 @@ int amdgpu_irq_init(struct amdgpu_device *adev) if (r) { adev->irq.installed = false; flush_work(&adev->hotplug_work); cancel_work_sync(&adev->reset_work); return r; } Loading @@ -264,6 +265,7 @@ void amdgpu_irq_fini(struct amdgpu_device *adev) if (adev->irq.msi_enabled) pci_disable_msi(adev->pdev); flush_work(&adev->hotplug_work); cancel_work_sync(&adev->reset_work); } for (i = 0; i < AMDGPU_MAX_IRQ_SRC_ID; ++i) { Loading drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +2 −4 Original line number Diff line number Diff line Loading @@ -459,10 +459,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file /* return all clocks in KHz */ dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; if (adev->pm.dpm_enabled) { dev_info.max_engine_clock = adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10; dev_info.max_memory_clock = adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk * 10; dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; } else { dev_info.max_engine_clock = adev->pm.default_sclk * 10; dev_info.max_memory_clock = adev->pm.default_mclk * 10; Loading Loading
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +2 −1 Original line number Diff line number Diff line Loading @@ -519,6 +519,7 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true, &duplicates); if (unlikely(r != 0)) { if (r != -ERESTARTSYS) DRM_ERROR("ttm_eu_reserve_buffers failed.\n"); goto error_free_pages; } Loading
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +4 −5 Original line number Diff line number Diff line Loading @@ -1959,6 +1959,7 @@ int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon) /* evict remaining vram memory */ amdgpu_bo_evict_vram(adev); amdgpu_atombios_scratch_regs_save(adev); pci_save_state(dev->pdev); if (suspend) { /* Shut down the device */ Loading Loading @@ -2010,6 +2011,7 @@ int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon) return r; } } amdgpu_atombios_scratch_regs_restore(adev); /* post card */ if (!amdgpu_card_posted(adev) || !resume) { Loading Loading @@ -2268,8 +2270,6 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev) } if (need_full_reset) { /* save scratch */ amdgpu_atombios_scratch_regs_save(adev); r = amdgpu_suspend(adev); retry: Loading @@ -2279,8 +2279,9 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev) amdgpu_display_stop_mc_access(adev, &save); amdgpu_wait_for_idle(adev, AMD_IP_BLOCK_TYPE_GMC); } amdgpu_atombios_scratch_regs_save(adev); r = amdgpu_asic_reset(adev); amdgpu_atombios_scratch_regs_restore(adev); /* post card */ amdgpu_atom_asic_init(adev->mode_info.atom_context); Loading @@ -2288,8 +2289,6 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev) dev_info(adev->dev, "GPU reset succeeded, trying to resume\n"); r = amdgpu_resume(adev); } /* restore scratch */ amdgpu_atombios_scratch_regs_restore(adev); } if (!r) { amdgpu_irq_gpu_reset_resume_helper(adev); Loading
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +1 −0 Original line number Diff line number Diff line Loading @@ -68,6 +68,7 @@ int amdgpu_fence_slab_init(void) void amdgpu_fence_slab_fini(void) { rcu_barrier(); kmem_cache_destroy(amdgpu_fence_slab); } /* Loading
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c +2 −0 Original line number Diff line number Diff line Loading @@ -239,6 +239,7 @@ int amdgpu_irq_init(struct amdgpu_device *adev) if (r) { adev->irq.installed = false; flush_work(&adev->hotplug_work); cancel_work_sync(&adev->reset_work); return r; } Loading @@ -264,6 +265,7 @@ void amdgpu_irq_fini(struct amdgpu_device *adev) if (adev->irq.msi_enabled) pci_disable_msi(adev->pdev); flush_work(&adev->hotplug_work); cancel_work_sync(&adev->reset_work); } for (i = 0; i < AMDGPU_MAX_IRQ_SRC_ID; ++i) { Loading
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +2 −4 Original line number Diff line number Diff line Loading @@ -459,10 +459,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file /* return all clocks in KHz */ dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; if (adev->pm.dpm_enabled) { dev_info.max_engine_clock = adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10; dev_info.max_memory_clock = adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk * 10; dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; } else { dev_info.max_engine_clock = adev->pm.default_sclk * 10; dev_info.max_memory_clock = adev->pm.default_mclk * 10; Loading