Commit 5f4ae270 authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915: Identify Cometlake platform 



Cometlake is a small refresh of Coffeelake, but since we have found out a
difference in the plaforms, we need to identify them as separate platforms.

Since we previously took Coffeelake/Cometlake as identical, update all
IS_COFFEELAKE() to also include IS_COMETLAKE().

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200602140541.5481-1-chris@chris-wilson.co.uk
parent c95ebab1

drivers/gpu/drm/i915/display/intel_csr.c

+3 −1
Original line number Diff line number Diff line
@@ -707,7 +707,9 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv) 
		csr->fw_path = GLK_CSR_PATH;

		csr->required_version = GLK_CSR_VERSION_REQUIRED;

		csr->max_fw_size = GLK_CSR_MAX_FW_SIZE;

	} else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {

	} else if (IS_KABYLAKE(dev_priv) ||

		   IS_COFFEELAKE(dev_priv) ||

		   IS_COMETLAKE(dev_priv)) {

		csr->fw_path = KBL_CSR_PATH;

		csr->required_version = KBL_CSR_VERSION_REQUIRED;

		csr->max_fw_size = KBL_CSR_MAX_FW_SIZE;

drivers/gpu/drm/i915/display/intel_ddi.c

+24 −10
Original line number Diff line number Diff line
@@ -722,10 +722,14 @@ skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) 
static const struct ddi_buf_trans *

kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)

{

	if (IS_KBL_ULX(dev_priv) || IS_CFL_ULX(dev_priv)) {

	if (IS_KBL_ULX(dev_priv) ||

	    IS_CFL_ULX(dev_priv) ||

	    IS_CML_ULX(dev_priv)) {

		*n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);

		return kbl_y_ddi_translations_dp;

	} else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {

	} else if (IS_KBL_ULT(dev_priv) ||

		   IS_CFL_ULT(dev_priv) ||

		   IS_CML_ULT(dev_priv)) {

		*n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);

		return kbl_u_ddi_translations_dp;

	} else {
@@ -738,12 +742,16 @@ static const struct ddi_buf_trans * 
skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)

{

	if (dev_priv->vbt.edp.low_vswing) {

		if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) ||

		    IS_CFL_ULX(dev_priv)) {

		if (IS_SKL_ULX(dev_priv) ||

		    IS_KBL_ULX(dev_priv) ||

		    IS_CFL_ULX(dev_priv) ||

		    IS_CML_ULX(dev_priv)) {

			*n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);

			return skl_y_ddi_translations_edp;

		} else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||

			   IS_CFL_ULT(dev_priv)) {

		} else if (IS_SKL_ULT(dev_priv) ||

			   IS_KBL_ULT(dev_priv) ||

			   IS_CFL_ULT(dev_priv) ||

			   IS_CML_ULT(dev_priv)) {

			*n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);

			return skl_u_ddi_translations_edp;

		} else {
@@ -752,7 +760,9 @@ skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) 
		}

	}



	if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))

	if (IS_KABYLAKE(dev_priv) ||

	    IS_COFFEELAKE(dev_priv) ||

	    IS_COMETLAKE(dev_priv))

		return kbl_get_buf_trans_dp(dev_priv, n_entries);

	else

		return skl_get_buf_trans_dp(dev_priv, n_entries);
@@ -761,8 +771,10 @@ skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) 
static const struct ddi_buf_trans *

skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)

{

	if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) ||

	    IS_CFL_ULX(dev_priv)) {

	if (IS_SKL_ULX(dev_priv) ||

	    IS_KBL_ULX(dev_priv) ||

	    IS_CFL_ULX(dev_priv) ||

	    IS_CML_ULX(dev_priv)) {

		*n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);

		return skl_y_ddi_translations_hdmi;

	} else {
@@ -784,7 +796,9 @@ static const struct ddi_buf_trans * 
intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,

			   enum port port, int *n_entries)

{

	if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {

	if (IS_KABYLAKE(dev_priv) ||

	    IS_COFFEELAKE(dev_priv) ||

	    IS_COMETLAKE(dev_priv)) {

		const struct ddi_buf_trans *ddi_translations =

			kbl_get_buf_trans_dp(dev_priv, n_entries);

		*n_entries = skl_buf_trans_num_entries(port, *n_entries);

drivers/gpu/drm/i915/display/intel_hdcp.c

+5 −2
Original line number Diff line number Diff line
@@ -1923,8 +1923,11 @@ static bool is_hdcp2_supported(struct drm_i915_private *dev_priv) 
	if (!IS_ENABLED(CONFIG_INTEL_MEI_HDCP))

		return false;



	return (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv) ||

		IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv));

	return (INTEL_GEN(dev_priv) >= 10 ||

		IS_GEMINILAKE(dev_priv) ||

		IS_KABYLAKE(dev_priv) ||

		IS_COFFEELAKE(dev_priv) ||

		IS_COMETLAKE(dev_priv));

}



void intel_hdcp_component_init(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/gt/intel_workarounds.c

+12 −6
Original line number Diff line number Diff line
@@ -361,7 +361,10 @@ static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine, 
			  HDC_FORCE_NON_COHERENT);



	/* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */

	if (IS_SKYLAKE(i915) || IS_KABYLAKE(i915) || IS_COFFEELAKE(i915))

	if (IS_SKYLAKE(i915) ||

	    IS_KABYLAKE(i915) ||

	    IS_COFFEELAKE(i915) ||

	    IS_COMETLAKE(i915))

		WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,

				  GEN8_SAMPLER_POWER_BYPASS_DIS);
@@ -636,7 +639,7 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, 
		icl_ctx_workarounds_init(engine, wal);

	else if (IS_CANNONLAKE(i915))

		cnl_ctx_workarounds_init(engine, wal);

	else if (IS_COFFEELAKE(i915))

	else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))

		cfl_ctx_workarounds_init(engine, wal);

	else if (IS_GEMINILAKE(i915))

		glk_ctx_workarounds_init(engine, wal);
@@ -706,7 +709,7 @@ static void 
gen9_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)

{

	/* WaDisableKillLogic:bxt,skl,kbl */

	if (!IS_COFFEELAKE(i915))

	if (!IS_COFFEELAKE(i915) && !IS_COMETLAKE(i915))

		wa_write_or(wal,

			    GAM_ECOCHK,

			    ECOCHK_DIS_TLB);
@@ -969,7 +972,7 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal) 
		icl_gt_workarounds_init(i915, wal);

	else if (IS_CANNONLAKE(i915))

		cnl_gt_workarounds_init(i915, wal);

	else if (IS_COFFEELAKE(i915))

	else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))

		cfl_gt_workarounds_init(i915, wal);

	else if (IS_GEMINILAKE(i915))

		glk_gt_workarounds_init(i915, wal);
@@ -1304,7 +1307,7 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine) 
		icl_whitelist_build(engine);

	else if (IS_CANNONLAKE(i915))

		cnl_whitelist_build(engine);

	else if (IS_COFFEELAKE(i915))

	else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))

		cfl_whitelist_build(engine);

	else if (IS_GEMINILAKE(i915))

		glk_whitelist_build(engine);
@@ -1515,7 +1518,10 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 
			     GEN9_FFSC_PERCTX_PREEMPT_CTRL);

	}



	if (IS_SKYLAKE(i915) || IS_KABYLAKE(i915) || IS_COFFEELAKE(i915)) {

	if (IS_SKYLAKE(i915) ||

	    IS_KABYLAKE(i915) ||

	    IS_COFFEELAKE(i915) ||

	    IS_COMETLAKE(i915)) {

		/* WaEnableGapsTsvCreditFix:skl,kbl,cfl */

		wa_write_or(wal,

			    GEN8_GARBCNTL,

drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c

+1 −1
Original line number Diff line number Diff line
@@ -55,7 +55,7 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw, 
	fw_def(TIGERLAKE,   0, guc_def(tgl, 35, 2, 0), huc_def(tgl,  7, 0, 12)) \

	fw_def(ELKHARTLAKE, 0, guc_def(ehl, 33, 0, 4), huc_def(ehl,  9, 0, 0)) \

	fw_def(ICELAKE,     0, guc_def(icl, 33, 0, 0), huc_def(icl,  9, 0, 0)) \

	fw_def(COFFEELAKE,  5, guc_def(cml, 33, 0, 0), huc_def(cml,  4, 0, 0)) \

	fw_def(COMETLAKE,   5, guc_def(cml, 33, 0, 0), huc_def(cml,  4, 0, 0)) \

	fw_def(COFFEELAKE,  0, guc_def(kbl, 33, 0, 0), huc_def(kbl,  4, 0, 0)) \

	fw_def(GEMINILAKE,  0, guc_def(glk, 33, 0, 0), huc_def(glk,  4, 0, 0)) \

	fw_def(KABYLAKE,    0, guc_def(kbl, 33, 0, 0), huc_def(kbl,  4, 0, 0)) \