Commit 5f41741a authored by Oak Zeng's avatar Oak Zeng Committed by Alex Deucher
Browse files

Revert "drm/amdgpu: workaround the TMR MC address issue (v2)" 



This reverts commit 2f055097.
2f055097 was a driver workaround
when PSP firmware was not ready. Now the PSP fw is ready so we
revert this driver workaround.

Signed-off-by: default avatarOak Zeng <Oak.Zeng@amd.com>
Reviewed-by: default avatarHarish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 839ede89

drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h

+0 −9
Original line number Diff line number Diff line
@@ -218,15 +218,6 @@ struct amdgpu_gmc { 
	 */

	u64			fb_start;

	u64			fb_end;

	/* In the case of use GART table for vmid0 FB access, [fb_start, fb_end]

	 * will be squeezed to GART aperture. But we have a PSP FW issue to fix

	 * for now. To temporarily workaround the PSP FW issue, added below two

	 * variables to remember the original fb_start/end to re-enable FB

	 * aperture to workaround the PSP FW issue. Will delete it after we

	 * get a proper PSP FW fix.

	 */

	u64			fb_start_original;

	u64			fb_end_original;

	unsigned		vram_width;

	u64			real_vram_size;

	int			vram_mtrr;

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

+0 −10
Original line number Diff line number Diff line
@@ -414,16 +414,6 @@ static int psp_tmr_init(struct psp_context *psp) 
				      AMDGPU_GEM_DOMAIN_VRAM,

				      &psp->tmr_bo, &psp->tmr_mc_addr, pptr);



	/* workaround the tmr_mc_addr:

	 * PSP requires an address in FB aperture. Right now driver produce

	 * tmr_mc_addr in the GART aperture. Convert it back to FB aperture

	 * for PSP. Will revert it after we get a fix from PSP FW.

	 */

	if (psp->adev->asic_type == CHIP_ALDEBARAN) {

		psp->tmr_mc_addr -= psp->adev->gmc.fb_start;

		psp->tmr_mc_addr += psp->adev->gmc.fb_start_original;

	}



	return ret;

}

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

+6 −15
Original line number Diff line number Diff line
@@ -140,14 +140,6 @@ static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev) 
	 * FB aperture and AGP aperture. Disable them.

	 */

	if (adev->gmc.pdb0_bo) {

		if (adev->asic_type == CHIP_ALDEBARAN) {

			WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_TOP, adev->gmc.fb_end_original >> 24);

			WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_BASE, adev->gmc.fb_start_original >> 24);

			WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, 0);

			WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, 0xFFFFFF);

			WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, adev->gmc.fb_start_original >> 18);

			WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, adev->gmc.fb_end_original >> 18);

		} else {

		WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_TOP, 0);

		WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_BASE, 0x00FFFFFF);

		WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, 0);
@@ -156,7 +148,6 @@ static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev) 
		WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0);

	}

}

}



static void gfxhub_v1_0_init_tlb_regs(struct amdgpu_device *adev)

{

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

+4 −6
Original line number Diff line number Diff line
@@ -47,8 +47,6 @@ static u64 mmhub_v1_7_get_fb_location(struct amdgpu_device *adev) 


	adev->gmc.fb_start = base;

	adev->gmc.fb_end = top;

	adev->gmc.fb_start_original = base;

	adev->gmc.fb_end_original = top;



	return base;

}
@@ -126,10 +124,10 @@ static void mmhub_v1_7_init_system_aperture_regs(struct amdgpu_device *adev) 
	if (adev->gmc.pdb0_bo) {

		WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_BOT, 0xFFFFFF);

		WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_TOP, 0);

		WREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_TOP, adev->gmc.fb_end_original >> 24);

		WREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_BASE, adev->gmc.fb_start_original >> 24);

		WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_LOW_ADDR, adev->gmc.fb_start_original >> 18);

		WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_HIGH_ADDR, adev->gmc.fb_end_original >> 18);

		WREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_TOP, 0);

		WREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_BASE, 0x00FFFFFF);

		WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_LOW_ADDR, 0x3FFFFFFF);

		WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0);

	}

	if (amdgpu_sriov_vf(adev))

		return;