Loading arch/parisc/kernel/pci.c +0 −18 Original line number Diff line number Diff line Loading @@ -171,24 +171,6 @@ void pcibios_set_master(struct pci_dev *dev) } void __init pcibios_init_bus(struct pci_bus *bus) { struct pci_dev *dev = bus->self; unsigned short bridge_ctl; /* We deal only with pci controllers and pci-pci bridges. */ if (!dev || (dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) return; /* PCI-PCI bridge - set the cache line and default latency (32) for primary and secondary buses. */ pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 32); pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bridge_ctl); bridge_ctl |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR; pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bridge_ctl); } /* * pcibios align resources() is called every time generic PCI code * wants to generate a new address. The process of looking for Loading Loading
arch/parisc/kernel/pci.c +0 −18 Original line number Diff line number Diff line Loading @@ -171,24 +171,6 @@ void pcibios_set_master(struct pci_dev *dev) } void __init pcibios_init_bus(struct pci_bus *bus) { struct pci_dev *dev = bus->self; unsigned short bridge_ctl; /* We deal only with pci controllers and pci-pci bridges. */ if (!dev || (dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) return; /* PCI-PCI bridge - set the cache line and default latency (32) for primary and secondary buses. */ pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 32); pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bridge_ctl); bridge_ctl |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR; pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bridge_ctl); } /* * pcibios align resources() is called every time generic PCI code * wants to generate a new address. The process of looking for Loading