Commit 5eeae247 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/gfx9: cache DB_DEBUG2 and make it available to userspace 



Userspace needs to query this value to work around a hw bug in
certain cases.

Acked-by: default avatarNicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 5452cf44

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+2 −0
Original line number Diff line number Diff line
@@ -867,6 +867,8 @@ struct amdgpu_gfx_config { 


	/* gfx configure feature */

	uint32_t double_offchip_lds_buf;

	/* cached value of DB_DEBUG2 */

	uint32_t db_debug2;

};



struct amdgpu_cu_info {

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+1 −0
Original line number Diff line number Diff line
@@ -1600,6 +1600,7 @@ static void gfx_v9_0_gpu_init(struct amdgpu_device *adev) 


	gfx_v9_0_setup_rb(adev);

	gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info);

	adev->gfx.config.db_debug2 = RREG32_SOC15(GC, 0, mmDB_DEBUG2);



	/* XXX SH_MEM regs */

	/* where to put LDS, scratch, GPUVM in FSA64 space */

drivers/gpu/drm/amd/amdgpu/soc15.c

+3 −0
Original line number Diff line number Diff line
@@ -287,6 +287,7 @@ static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = { 
	{ SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},

	{ SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},

	{ SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},

	{ SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)},

};



static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
@@ -315,6 +316,8 @@ static uint32_t soc15_get_register_value(struct amdgpu_device *adev, 
	} else {

		if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))

			return adev->gfx.config.gb_addr_config;

		else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))

			return adev->gfx.config.db_debug2;

		return RREG32(reg_offset);

	}

}