Commit 5edf5b51 authored by Biju Das's avatar Biju Das Committed by Geert Uytterhoeven
Browse files

clk: renesas: r9a09g011: Add USB clock and reset entries 



Add USB clock and reset entries to CPG driver.

Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20221212172804.1277751-2-biju.das.jz@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent d459f557

drivers/clk/renesas/r9a09g011-cpg.c

+21 −0
Original line number Diff line number Diff line
@@ -23,10 +23,12 @@ 


#define DIV_A		DDIV_PACK(0x200, 0, 3)

#define DIV_B		DDIV_PACK(0x204, 0, 2)

#define DIV_D		DDIV_PACK(0x204, 4, 2)

#define DIV_E		DDIV_PACK(0x204, 8, 1)

#define DIV_W		DDIV_PACK(0x328, 0, 3)



#define SEL_B		SEL_PLL_PACK(0x214, 0, 1)

#define SEL_D		SEL_PLL_PACK(0x214, 1, 1)

#define SEL_E		SEL_PLL_PACK(0x214, 2, 1)

#define SEL_W0		SEL_PLL_PACK(0x32C, 0, 1)
@@ -50,10 +52,12 @@ enum clk_ids { 
	CLK_PLL4,

	CLK_DIV_A,

	CLK_DIV_B,

	CLK_DIV_D,

	CLK_DIV_E,

	CLK_DIV_W,

	CLK_SEL_B,

	CLK_SEL_B_D2,

	CLK_SEL_D,

	CLK_SEL_E,

	CLK_SEL_W0,
@@ -81,6 +85,13 @@ static const struct clk_div_table dtable_divb[] = { 
	{0, 0},

};



static const struct clk_div_table dtable_divd[] = {

	{0, 1},

	{1, 2},

	{2, 4},

	{0, 0},

};



static const struct clk_div_table dtable_divw[] = {

	{0, 6},

	{1, 7},
@@ -94,6 +105,7 @@ static const struct clk_div_table dtable_divw[] = { 


/* Mux clock tables */

static const char * const sel_b[] = { ".main", ".divb" };

static const char * const sel_d[] = { ".main", ".divd" };

static const char * const sel_e[] = { ".main", ".dive" };

static const char * const sel_w[] = { ".main", ".divw" };
@@ -115,10 +127,12 @@ static const struct cpg_core_clk r9a09g011_core_clks[] __initconst = { 


	DEF_DIV_RO(".diva",	CLK_DIV_A,	CLK_PLL1,	DIV_A,	dtable_diva),

	DEF_DIV_RO(".divb",	CLK_DIV_B,	CLK_PLL2_400,	DIV_B,	dtable_divb),

	DEF_DIV_RO(".divd",	CLK_DIV_D,	CLK_PLL2_200,	DIV_D,	dtable_divd),

	DEF_DIV_RO(".dive",	CLK_DIV_E,	CLK_PLL2_100,	DIV_E,	NULL),

	DEF_DIV_RO(".divw",	CLK_DIV_W,	CLK_PLL4,	DIV_W,	dtable_divw),



	DEF_MUX_RO(".selb",	CLK_SEL_B,	SEL_B,		sel_b),

	DEF_MUX_RO(".seld",	CLK_SEL_D,	SEL_D,		sel_d),

	DEF_MUX_RO(".sele",	CLK_SEL_E,	SEL_E,		sel_e),

	DEF_MUX(".selw0",	CLK_SEL_W0,	SEL_W0,		sel_w),
@@ -131,6 +145,9 @@ static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = { 
	DEF_COUPLED("eth_axi",	R9A09G011_ETH0_CLK_AXI,	 CLK_PLL2_200, 0x40c, 8),

	DEF_COUPLED("eth_chi",	R9A09G011_ETH0_CLK_CHI,	 CLK_PLL2_100, 0x40c, 8),

	DEF_MOD("eth_clk_gptp",	R9A09G011_ETH0_GPTP_EXT, CLK_PLL2_100, 0x40c, 9),

	DEF_MOD("usb_aclk_h",	R9A09G011_USB_ACLK_H,	 CLK_SEL_D,    0x40c, 4),

	DEF_MOD("usb_aclk_p",	R9A09G011_USB_ACLK_P,	 CLK_SEL_D,    0x40c, 5),

	DEF_MOD("usb_pclk",	R9A09G011_USB_PCLK,	 CLK_SEL_E,    0x40c, 6),

	DEF_MOD("syc_cnt_clk",	R9A09G011_SYC_CNT_CLK,	 CLK_MAIN_24,  0x41c, 12),

	DEF_MOD("iic_pclk0",	R9A09G011_IIC_PCLK0,	 CLK_SEL_E,    0x420, 12),

	DEF_MOD("cperi_grpb",	R9A09G011_CPERI_GRPB_PCLK, CLK_SEL_E,  0x424, 0),
@@ -169,6 +186,10 @@ static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = { 


static const struct rzg2l_reset r9a09g011_resets[] = {

	DEF_RST(R9A09G011_PFC_PRESETN,		0x600, 2),

	DEF_RST(R9A09G011_USB_PRESET_N,		0x608, 7),

	DEF_RST(R9A09G011_USB_DRD_RESET,	0x608, 8),

	DEF_RST(R9A09G011_USB_ARESETN_P,	0x608, 9),

	DEF_RST(R9A09G011_USB_ARESETN_H,	0x608, 10),

	DEF_RST_MON(R9A09G011_ETH0_RST_HW_N,	0x608, 11, 11),

	DEF_RST_MON(R9A09G011_SYC_RST_N,	0x610, 9,  13),

	DEF_RST(R9A09G011_TIM_GPB_PRESETN,	0x614, 1),