Commit 5edc3c61 authored by Ian Rogers's avatar Ian Rogers Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events intel: Update events for TremontX 

Move from v1.17 to v1.19.

The change:

  https://github.com/intel/event-converter-for-linux-perf/commit/fc680410402e394eed6a1ebd909c9f649d3ed3ef



moved certain "other" type of events in to the cache, memory and
pipeline topics. Update the perf JSON files for this change.

Reviewed-by: default avatarXing Zhengjun <zhengjun.xing@linux.intel.com>
Signed-off-by: default avatarIan Rogers <irogers@google.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.garry@huawei.com>
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Link: https://lore.kernel.org/r/20220317182858.484474-8-irogers@google.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 42e80e1a

tools/perf/pmu-events/arch/x86/tremontx/cache.json

+835 −4

File changed.

Preview size limit exceeded, changes collapsed.

tools/perf/pmu-events/arch/x86/tremontx/floating-point.json

+12 −0
Original line number Diff line number Diff line
@@ -10,6 +10,18 @@ 
        "SampleAfterValue": "200003",

        "UMask": "0x2"

    },

    {

        "BriefDescription": "Counts the number of floating point operations retired that required microcode assist.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3",

        "EventCode": "0xc3",

        "EventName": "MACHINE_CLEARS.FP_ASSIST",

        "PDIR_COUNTER": "na",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops.",

        "SampleAfterValue": "20003",

        "UMask": "0x4"

    },

    {

        "BriefDescription": "Counts the number of floating point divide uops retired (x87 and SSE, including x87 sqrt).",

        "CollectPEBSRecord": "2",

tools/perf/pmu-events/arch/x86/tremontx/memory.json

+22 −37
Original line number Diff line number Diff line
@@ -10,6 +10,28 @@ 
        "SampleAfterValue": "20003",

        "UMask": "0x2"

    },

    {

        "BriefDescription": "Counts the number of misaligned load uops that are 4K page splits.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3",

        "EventCode": "0x13",

        "EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT",

        "PEBS": "1",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "200003",

        "UMask": "0x2"

    },

    {

        "BriefDescription": "Counts the number of misaligned store uops that are 4K page splits.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3",

        "EventCode": "0x13",

        "EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT",

        "PEBS": "1",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "200003",

        "UMask": "0x4"

    },

    {

        "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.",

        "Counter": "0,1,2,3",
@@ -18,7 +40,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x2184000044",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -30,7 +51,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x2184000044",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -42,7 +62,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x3002184000000",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -54,7 +73,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x3002184000000",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -66,7 +84,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x2184000004",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -78,7 +95,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x2184000004",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -90,7 +106,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x2184000001",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -102,7 +117,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x2184000001",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -114,7 +128,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x2184000001",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -126,7 +139,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x2184000001",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -138,7 +150,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x2184000002",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -150,7 +161,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x2184000002",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -162,7 +172,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x802184000000",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -174,7 +183,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x802184000000",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -186,7 +194,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x2184000040",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -198,7 +205,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x2184000040",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -210,7 +216,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x2184000010",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -222,7 +227,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x2184000010",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -234,7 +238,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x2184000020",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -246,7 +249,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x2184000020",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -258,7 +260,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x1002184000000",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -270,7 +271,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x1002184000000",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -282,7 +282,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x2002184000000",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -294,7 +293,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x2002184000000",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -306,7 +304,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x2184008000",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -318,7 +315,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x2184008000",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -330,7 +326,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x402184000000",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -342,7 +337,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x402184000000",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -354,7 +348,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x2184000470",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -366,7 +359,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x2184000477",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -378,7 +370,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x2184000477",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -390,7 +381,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x2184000800",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -402,7 +392,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x2184000800",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -414,7 +403,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x102184000000",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -426,7 +414,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x102184000000",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -438,7 +425,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x202184000000",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },
@@ -450,7 +436,6 @@ 
        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x202184000000",

        "Offcore": "1",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    }

tools/perf/pmu-events/arch/x86/tremontx/other.json

+128 −1234

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tools/perf/pmu-events/arch/x86/tremontx/pipeline.json

+320 −0

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