Commit 5ed2b638 authored by Luca Weiss's avatar Luca Weiss Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: sm6350: Use specific qmpphy compatible 



The sc7180 phy compatible works fine for some cases, but it turns out
sm6350 does need proper phy configuration in the driver, so use the
newly added sm6350 compatible.

Because the sm6350 compatible is using the new binding, we need to
change the node quite a bit to match it.

This fixes qmpphy init when no USB cable is plugged in during bootloader
stage.

Reviewed-by: default avatarJohan Hovold <johan+linaro@kernel.org>
Signed-off-by: default avatarLuca Weiss <luca.weiss@fairphone.com>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230120-sm6350-usbphy-v4-3-4d700a90ba16@fairphone.com
parent 77b1278e

arch/arm64/boot/dts/qcom/sm6350.dtsi

+16 −38
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ 
#include <dt-bindings/interconnect/qcom,sm6350.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/mailbox/qcom-ipcc.h>

#include <dt-bindings/phy/phy-qcom-qmp.h>

#include <dt-bindings/power/qcom-rpmpd.h>

#include <dt-bindings/soc/qcom,rpmh-rsc.h>
@@ -1315,49 +1316,26 @@ 
			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;

		};



		usb_1_qmpphy: phy@88e9000 {

			compatible = "qcom,sc7180-qmp-usb3-dp-phy";

			reg = <0 0x088e9000 0 0x200>,

			      <0 0x088e8000 0 0x40>,

			      <0 0x088ea000 0 0x200>;

			status = "disabled";

			#address-cells = <2>;

			#size-cells = <2>;

			ranges;

		usb_1_qmpphy: phy@88e8000 {

			compatible = "qcom,sm6350-qmp-usb3-dp-phy";

			reg = <0 0x088e8000 0 0x3000>;



			clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,

				 <&xo_board>,

				 <&rpmhcc RPMH_QLINK_CLK>,

				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;

			clock-names = "aux", "cfg_ahb", "ref", "com_aux";

				 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,

				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,

				 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;

			clock-names = "aux", "ref", "com_aux", "usb3_pipe";



			resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,

				 <&gcc GCC_USB3_PHY_PRIM_BCR>;

			reset-names = "phy", "common";

			power-domains = <&gcc USB30_PRIM_GDSC>;



			usb_1_ssphy: usb3-phy@88e9200 {

				reg = <0 0x088e9200 0 0x200>,

				      <0 0x088e9400 0 0x200>,

				      <0 0x088e9c00 0 0x400>,

				      <0 0x088e9600 0 0x200>,

				      <0 0x088e9800 0 0x200>,

				      <0 0x088e9a00 0 0x100>;

				#clock-cells = <0>;

				#phy-cells = <0>;

				clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;

				clock-names = "pipe0";

				clock-output-names = "usb3_phy_pipe_clk_src";

			};

			resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,

				 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;

			reset-names = "phy", "common";



			dp_phy: dp-phy@88ea200 {

				reg = <0 0x088ea200 0 0x200>,

				      <0 0x088ea400 0 0x200>,

				      <0 0x088eaa00 0 0x200>,

				      <0 0x088ea600 0 0x200>,

				      <0 0x088ea800 0 0x200>;

				#phy-cells = <0>;

			#clock-cells = <1>;

			};

			#phy-cells = <1>;



			status = "disabled";

		};



		dc_noc: interconnect@9160000 {
@@ -1431,7 +1409,7 @@ 
				snps,dis_enblslpm_quirk;

				snps,has-lpm-erratum;

				snps,hird-threshold = /bits/ 8 <0x10>;

				phys = <&usb_1_hsphy>, <&usb_1_ssphy>;

				phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;

				phy-names = "usb2-phy", "usb3-phy";

			};

		};