Commit 5e85eba6 authored by Vidya Sagar's avatar Vidya Sagar Committed by Bjorn Helgaas
Browse files

PCI/ASPM: Refactor L1 PM Substates Control Register programming 

Refactor the code to extract the common code to program Control
Registers 1 and 2 of the L1 PM Substates capability to a new function
aspm_program_l1ss() and call it for both parent and child devices.

[bhelgaas: squash in update to preserve fields we're not updating from
https://lore.kernel.org/r/36fa13c5-e0f8-022f-77f7-7908e4df98b8@nvidia.com]
Link: https://lore.kernel.org/r/20220913131822.16557-2-vidyas@nvidia.com


Signed-off-by: default avatarVidya Sagar <vidyas@nvidia.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
parent 568035b0

drivers/pci/pcie/aspm.c

+40 −34
Original line number Diff line number Diff line
@@ -455,6 +455,31 @@ static void pci_clear_and_set_dword(struct pci_dev *pdev, int pos, 
	pci_write_config_dword(pdev, pos, val);

}



static void aspm_program_l1ss(struct pci_dev *dev, u32 ctl1, u32 ctl2)

{

	u16 l1ss = dev->l1ss;

	u32 l1_2_enable;



	/*

	 * Per PCIe r6.0, sec 5.5.4, T_POWER_ON in PCI_L1SS_CTL2 must be

	 * programmed prior to setting the L1.2 enable bits in PCI_L1SS_CTL1.

	 */

	pci_write_config_dword(dev, l1ss + PCI_L1SS_CTL2, ctl2);



	/*

	 * In addition, Common_Mode_Restore_Time and LTR_L1.2_THRESHOLD in

	 * PCI_L1SS_CTL1 must be programmed *before* setting the L1.2

	 * enable bits, even though they're all in PCI_L1SS_CTL1.

	 */

	l1_2_enable = ctl1 & PCI_L1SS_CTL1_L1_2_MASK;

	ctl1 &= ~PCI_L1SS_CTL1_L1_2_MASK;



	pci_write_config_dword(dev, l1ss + PCI_L1SS_CTL1, ctl1);

	if (l1_2_enable)

		pci_write_config_dword(dev, l1ss + PCI_L1SS_CTL1,

				       ctl1 | l1_2_enable);

}



/* Calculate L1.2 PM substate timing parameters */

static void aspm_calc_l1ss_info(struct pcie_link_state *link,

				u32 parent_l1ss_cap, u32 child_l1ss_cap)
@@ -464,7 +489,6 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link, 
	u32 t_common_mode, t_power_on, l1_2_threshold, scale, value;

	u32 ctl1 = 0, ctl2 = 0;

	u32 pctl1, pctl2, cctl1, cctl2;

	u32 pl1_2_enables, cl1_2_enables;



	if (!(link->aspm_support & ASPM_STATE_L1_2_MASK))

		return;
@@ -513,39 +537,21 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link, 
	    ctl2 == pctl2 && ctl2 == cctl2)

		return;



	/* Disable L1.2 while updating.  See PCIe r5.0, sec 5.5.4, 7.8.3.3 */

	pl1_2_enables = pctl1 & PCI_L1SS_CTL1_L1_2_MASK;

	cl1_2_enables = cctl1 & PCI_L1SS_CTL1_L1_2_MASK;



	if (pl1_2_enables || cl1_2_enables) {

		pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1,

					PCI_L1SS_CTL1_L1_2_MASK, 0);

		pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,

					PCI_L1SS_CTL1_L1_2_MASK, 0);

	}



	/* Program T_POWER_ON times in both ports */

	pci_write_config_dword(parent, parent->l1ss + PCI_L1SS_CTL2, ctl2);

	pci_write_config_dword(child, child->l1ss + PCI_L1SS_CTL2, ctl2);



	/* Program Common_Mode_Restore_Time in upstream device */

	pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,

				PCI_L1SS_CTL1_CM_RESTORE_TIME, ctl1);



	/* Program LTR_L1.2_THRESHOLD time in both ports */

	pci_clear_and_set_dword(parent,	parent->l1ss + PCI_L1SS_CTL1,

	pctl1 &= ~(PCI_L1SS_CTL1_CM_RESTORE_TIME |

		   PCI_L1SS_CTL1_LTR_L12_TH_VALUE |

				PCI_L1SS_CTL1_LTR_L12_TH_SCALE, ctl1);

	pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1,

		   PCI_L1SS_CTL1_LTR_L12_TH_SCALE);

	pctl1 |= (ctl1 & (PCI_L1SS_CTL1_CM_RESTORE_TIME |

			  PCI_L1SS_CTL1_LTR_L12_TH_VALUE |

				PCI_L1SS_CTL1_LTR_L12_TH_SCALE, ctl1);

			  PCI_L1SS_CTL1_LTR_L12_TH_SCALE));

	aspm_program_l1ss(parent, pctl1, ctl2);



	if (pl1_2_enables || cl1_2_enables) {

		pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1, 0,

					pl1_2_enables);

		pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1, 0,

					cl1_2_enables);

	}

	cctl1 &= ~(PCI_L1SS_CTL1_CM_RESTORE_TIME |

		   PCI_L1SS_CTL1_LTR_L12_TH_VALUE |

		   PCI_L1SS_CTL1_LTR_L12_TH_SCALE);

	cctl1 |= (ctl1 & (PCI_L1SS_CTL1_CM_RESTORE_TIME |

			  PCI_L1SS_CTL1_LTR_L12_TH_VALUE |

			  PCI_L1SS_CTL1_LTR_L12_TH_SCALE));

	aspm_program_l1ss(child, cctl1, ctl2);

}



static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)