Commit 5e7665b5 authored by Bjorn Andersson's avatar Bjorn Andersson Committed by Rob Clark
Browse files

drm/msm/adreno: Add Adreno A690 support 



Introduce support for the Adreno A690, found in Qualcomm SC8280XP.

Tested-by: default avatarSteev Klimaszewski <steev@kali.org>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: default avatarBjorn Andersson <quic_bjorande@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/540335/


Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent 171f580e

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

+111 −2
Original line number Diff line number Diff line
@@ -588,6 +588,63 @@ const struct adreno_reglist a660_hwcg[] = { 
	{},

};



const struct adreno_reglist a690_hwcg[] = {

	{REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},

	{REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},

	{REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},

	{REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},

	{REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},

	{REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},

	{REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},

	{REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},

	{REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},

	{REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},

	{REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},

	{REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},

	{REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},

	{REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},

	{REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},

	{REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},

	{REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},

	{REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},

	{REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},

	{REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},

	{REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},

	{REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},

	{REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},

	{REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},

	{REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},

	{REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},

	{REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},

	{REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},

	{REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},

	{REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},

	{REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},

	{REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},

	{REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},

	{REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},

	{REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},

	{REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},

	{REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},

	{REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},

	{REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},

	{REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000},

	{REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},

	{REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},

	{REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},

	{REG_A6XX_RBBM_CLOCK_CNTL, 0x8AA8AA82},

	{REG_A6XX_RBBM_ISDB_CNT, 0x00000182},

	{REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},

	{REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},

	{REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},

	{REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},

	{REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},

	{REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, 0x20200},

	{REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, 0x10111},

	{REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL, 0x5555},

	{}

};



static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)

{

	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
@@ -747,6 +804,45 @@ static const u32 a660_protect[] = { 
	A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */

};



/* These are for a690 */

static const u32 a690_protect[] = {

	A6XX_PROTECT_RDONLY(0x00000, 0x004ff),

	A6XX_PROTECT_RDONLY(0x00501, 0x00001),

	A6XX_PROTECT_RDONLY(0x0050b, 0x002f4),

	A6XX_PROTECT_NORDWR(0x0050e, 0x00000),

	A6XX_PROTECT_NORDWR(0x00510, 0x00000),

	A6XX_PROTECT_NORDWR(0x00534, 0x00000),

	A6XX_PROTECT_NORDWR(0x00800, 0x00082),

	A6XX_PROTECT_NORDWR(0x008a0, 0x00008),

	A6XX_PROTECT_NORDWR(0x008ab, 0x00024),

	A6XX_PROTECT_RDONLY(0x008d0, 0x000bc),

	A6XX_PROTECT_NORDWR(0x00900, 0x0004d),

	A6XX_PROTECT_NORDWR(0x0098d, 0x00272),

	A6XX_PROTECT_NORDWR(0x00e00, 0x00001),

	A6XX_PROTECT_NORDWR(0x00e03, 0x0000c),

	A6XX_PROTECT_NORDWR(0x03c00, 0x000c3),

	A6XX_PROTECT_RDONLY(0x03cc4, 0x01fff),

	A6XX_PROTECT_NORDWR(0x08630, 0x001cf),

	A6XX_PROTECT_NORDWR(0x08e00, 0x00000),

	A6XX_PROTECT_NORDWR(0x08e08, 0x00008),

	A6XX_PROTECT_NORDWR(0x08e50, 0x0001f),

	A6XX_PROTECT_NORDWR(0x08e80, 0x0027f),

	A6XX_PROTECT_NORDWR(0x09624, 0x001db),

	A6XX_PROTECT_NORDWR(0x09e60, 0x00011),

	A6XX_PROTECT_NORDWR(0x09e78, 0x00187),

	A6XX_PROTECT_NORDWR(0x0a630, 0x001cf),

	A6XX_PROTECT_NORDWR(0x0ae02, 0x00000),

	A6XX_PROTECT_NORDWR(0x0ae50, 0x0012f),

	A6XX_PROTECT_NORDWR(0x0b604, 0x00000),

	A6XX_PROTECT_NORDWR(0x0b608, 0x00006),

	A6XX_PROTECT_NORDWR(0x0be02, 0x00001),

	A6XX_PROTECT_NORDWR(0x0be20, 0x0015f),

	A6XX_PROTECT_NORDWR(0x0d000, 0x005ff),

	A6XX_PROTECT_NORDWR(0x0f000, 0x00bff),

	A6XX_PROTECT_RDONLY(0x0fc00, 0x01fff),

	A6XX_PROTECT_NORDWR(0x11c00, 0x00000), /*note: infiite range */

};



static void a6xx_set_cp_protect(struct msm_gpu *gpu)

{

	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
@@ -758,6 +854,11 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) 
		count = ARRAY_SIZE(a650_protect);

		count_max = 48;

		BUILD_BUG_ON(ARRAY_SIZE(a650_protect) > 48);

	} else if (adreno_is_a690(adreno_gpu)) {

		regs = a690_protect;

		count = ARRAY_SIZE(a690_protect);

		count_max = 48;

		BUILD_BUG_ON(ARRAY_SIZE(a690_protect) > 48);

	} else if (adreno_is_a660_family(adreno_gpu)) {

		regs = a660_protect;

		count = ARRAY_SIZE(a660_protect);
@@ -806,6 +907,13 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) 
		uavflagprd_inv = 2;

	}



	if (adreno_is_a690(adreno_gpu)) {

		lower_bit = 2;

		amsbc = 1;

		rgb565_predicator = 1;

		uavflagprd_inv = 2;

	}



	if (adreno_is_7c3(adreno_gpu)) {

		lower_bit = 1;

		amsbc = 1;
@@ -1084,7 +1192,7 @@ static int hw_init(struct msm_gpu *gpu) 
	/* Setting the primFifo thresholds default values,

	 * and vccCacheSkipDis=1 bit (0x200) for A640 and newer

	*/

	if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu))

	if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu) || adreno_is_a690(adreno_gpu))

		gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200);

	else if (adreno_is_a640_family(adreno_gpu) || adreno_is_7c3(adreno_gpu))

		gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200200);
@@ -1994,6 +2102,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) 
	info = adreno_info(config->rev);



	if (info && (info->revn == 650 || info->revn == 660 ||

		     info->revn == 690 ||

		     adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), info->rev)))

		adreno_gpu->base.hw_apriv = true;

drivers/gpu/drm/msm/adreno/a6xx_hfi.c

+33 −0
Original line number Diff line number Diff line
@@ -414,6 +414,37 @@ static void a650_build_bw_table(struct a6xx_hfi_msg_bw_table *msg) 
	msg->cnoc_cmds_data[1][0] =  0x60000001;

}



static void a690_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)

{

	/*

	 * Send a single "off" entry just to get things running

	 * TODO: bus scaling

	 */

	msg->bw_level_num = 1;



	msg->ddr_cmds_num = 3;

	msg->ddr_wait_bitmask = 0x01;



	msg->ddr_cmds_addrs[0] = 0x50004;

	msg->ddr_cmds_addrs[1] = 0x50000;

	msg->ddr_cmds_addrs[2] = 0x500ac;



	msg->ddr_cmds_data[0][0] =  0x40000000;

	msg->ddr_cmds_data[0][1] =  0x40000000;

	msg->ddr_cmds_data[0][2] =  0x40000000;



	/*

	 * These are the CX (CNOC) votes - these are used by the GMU but the

	 * votes are known and fixed for the target

	 */

	msg->cnoc_cmds_num = 1;

	msg->cnoc_wait_bitmask = 0x01;



	msg->cnoc_cmds_addrs[0] = 0x5003c;

	msg->cnoc_cmds_data[0][0] =  0x40000000;

	msg->cnoc_cmds_data[1][0] =  0x60000001;

}



static void a660_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)

{

	/*
@@ -531,6 +562,8 @@ static int a6xx_hfi_send_bw_table(struct a6xx_gmu *gmu) 
		adreno_7c3_build_bw_table(&msg);

	else if (adreno_is_a660(adreno_gpu))

		a660_build_bw_table(&msg);

	else if (adreno_is_a690(adreno_gpu))

		a690_build_bw_table(&msg);

	else

		a6xx_build_bw_table(&msg);

drivers/gpu/drm/msm/adreno/adreno_device.c

+14 −0
Original line number Diff line number Diff line
@@ -355,6 +355,20 @@ static const struct adreno_info gpulist[] = { 
		.init = a6xx_gpu_init,

		.zapfw = "a640_zap.mdt",

		.hwcg = a640_hwcg,

	}, {

		.rev = ADRENO_REV(6, 9, 0, ANY_ID),

		.revn = 690,

		.name = "A690",

		.fw = {

			[ADRENO_FW_SQE] = "a660_sqe.fw",

			[ADRENO_FW_GMU] = "a690_gmu.bin",

		},

		.gmem = SZ_4M,

		.inactive_period = DRM_MSM_INACTIVE_PERIOD,

		.init = a6xx_gpu_init,

		.zapfw = "a690_zap.mdt",

		.hwcg = a690_hwcg,

		.address_space_size = SZ_16G,

	},

};

drivers/gpu/drm/msm/adreno/adreno_gpu.h

+8 −3
Original line number Diff line number Diff line
@@ -55,7 +55,7 @@ struct adreno_reglist { 
	u32 value;

};



extern const struct adreno_reglist a615_hwcg[], a630_hwcg[], a640_hwcg[], a650_hwcg[], a660_hwcg[];

extern const struct adreno_reglist a615_hwcg[], a630_hwcg[], a640_hwcg[], a650_hwcg[], a660_hwcg[], a690_hwcg[];



struct adreno_info {

	struct adreno_rev rev;
@@ -272,6 +272,11 @@ static inline int adreno_is_a660(struct adreno_gpu *gpu) 
	return gpu->revn == 660;

}



static inline int adreno_is_a690(struct adreno_gpu *gpu)

{

	return gpu->revn == 690;

};



/* check for a615, a616, a618, a619 or any derivatives */

static inline int adreno_is_a615_family(struct adreno_gpu *gpu)

{
@@ -280,7 +285,7 @@ static inline int adreno_is_a615_family(struct adreno_gpu *gpu) 


static inline int adreno_is_a660_family(struct adreno_gpu *gpu)

{

	return adreno_is_a660(gpu) || adreno_is_7c3(gpu);

	return adreno_is_a660(gpu) || adreno_is_a690(gpu) || adreno_is_7c3(gpu);

}



/* check for a650, a660, or any derivatives */