Commit 5e64b862 authored by Mark Brown's avatar Mark Brown Committed by Catalin Marinas
Browse files

arm64/sme: Basic enumeration support 



This patch introduces basic cpufeature support for discovering the presence
of the Scalable Matrix Extension.

Signed-off-by: default avatarMark Brown <broonie@kernel.org>
Reviewed-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20220419112247.711548-9-broonie@kernel.org


Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent b2cf6a23

Documentation/arm64/elf_hwcaps.rst

+33 −0
Original line number Diff line number Diff line
@@ -264,6 +264,39 @@ HWCAP2_MTE3 
    Functionality implied by ID_AA64PFR1_EL1.MTE == 0b0011, as described

    by Documentation/arm64/memory-tagging-extension.rst.



HWCAP2_SME



    Functionality implied by ID_AA64PFR1_EL1.SME == 0b0001, as described

    by Documentation/arm64/sme.rst.



HWCAP2_SME_I16I64



    Functionality implied by ID_AA64SMFR0_EL1.I16I64 == 0b1111.



HWCAP2_SME_F64F64



    Functionality implied by ID_AA64SMFR0_EL1.F64F64 == 0b1.



HWCAP2_SME_I8I32



    Functionality implied by ID_AA64SMFR0_EL1.I8I32 == 0b1111.



HWCAP2_SME_F16F32



    Functionality implied by ID_AA64SMFR0_EL1.F16F32 == 0b1.



HWCAP2_SME_B16F32



    Functionality implied by ID_AA64SMFR0_EL1.B16F32 == 0b1.



HWCAP2_SME_F32F32



    Functionality implied by ID_AA64SMFR0_EL1.F32F32 == 0b1.



HWCAP2_SME_FA64



    Functionality implied by ID_AA64SMFR0_EL1.FA64 == 0b1.



4. Unused AT_HWCAP bits

-----------------------

arch/arm64/include/asm/cpu.h

+1 −0
Original line number Diff line number Diff line
@@ -58,6 +58,7 @@ struct cpuinfo_arm64 { 
	u64		reg_id_aa64pfr0;

	u64		reg_id_aa64pfr1;

	u64		reg_id_aa64zfr0;

	u64		reg_id_aa64smfr0;



	struct cpuinfo_32bit	aarch32;

arch/arm64/include/asm/cpufeature.h

+12 −0
Original line number Diff line number Diff line
@@ -759,6 +759,18 @@ static __always_inline bool system_supports_sve(void) 
		cpus_have_const_cap(ARM64_SVE);

}



static __always_inline bool system_supports_sme(void)

{

	return IS_ENABLED(CONFIG_ARM64_SME) &&

		cpus_have_const_cap(ARM64_SME);

}



static __always_inline bool system_supports_fa64(void)

{

	return IS_ENABLED(CONFIG_ARM64_SME) &&

		cpus_have_const_cap(ARM64_SME_FA64);

}



static __always_inline bool system_supports_cnp(void)

{

	return IS_ENABLED(CONFIG_ARM64_CNP) &&

arch/arm64/include/asm/fpsimd.h

+2 −0
Original line number Diff line number Diff line
@@ -74,6 +74,8 @@ extern void sve_set_vq(unsigned long vq_minus_1); 


struct arm64_cpu_capabilities;

extern void sve_kernel_enable(const struct arm64_cpu_capabilities *__unused);

extern void sme_kernel_enable(const struct arm64_cpu_capabilities *__unused);

extern void fa64_kernel_enable(const struct arm64_cpu_capabilities *__unused);



extern u64 read_zcr_features(void);

arch/arm64/include/asm/hwcap.h

+8 −0
Original line number Diff line number Diff line
@@ -109,6 +109,14 @@ 
#define KERNEL_HWCAP_AFP		__khwcap2_feature(AFP)

#define KERNEL_HWCAP_RPRES		__khwcap2_feature(RPRES)

#define KERNEL_HWCAP_MTE3		__khwcap2_feature(MTE3)

#define KERNEL_HWCAP_SME		__khwcap2_feature(SME)

#define KERNEL_HWCAP_SME_I16I64		__khwcap2_feature(SME_I16I64)

#define KERNEL_HWCAP_SME_F64F64		__khwcap2_feature(SME_F64F64)

#define KERNEL_HWCAP_SME_I8I32		__khwcap2_feature(SME_I8I32)

#define KERNEL_HWCAP_SME_F16F32		__khwcap2_feature(SME_F16F32)

#define KERNEL_HWCAP_SME_B16F32		__khwcap2_feature(SME_B16F32)

#define KERNEL_HWCAP_SME_F32F32		__khwcap2_feature(SME_F32F32)

#define KERNEL_HWCAP_SME_FA64		__khwcap2_feature(SME_FA64)



/*

 * This yields a mask that user programs can use to figure out what