Commit 5e5c636c authored by Lorenzo Pieralisi's avatar Lorenzo Pieralisi Committed by Marc Zyngier
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dt-bindings: interrupt-controller: arm,gic-v3: Add dma-noncoherent property 



The GIC v3 specifications allow redistributors and ITSes interconnect
ports used to access memory to be wired up in a way that makes the
respective initiators/memory observers non-coherent.

Add the standard dma-noncoherent property to the GICv3 bindings to
allow firmware to describe the redistributors/ITSes components and
interconnect ports behaviour in system designs where the redistributors
and ITSes are not coherent with the CPU.

Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarLorenzo Pieralisi <lpieralisi@kernel.org>
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20231006125929.48591-2-lpieralisi@kernel.org
parent 977f7c2b

Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml

+12 −0
Original line number Diff line number Diff line
@@ -106,6 +106,12 @@ properties: 
    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 4096



  dma-noncoherent:

    description:

      Present if the GIC redistributors permit programming shareability

      and cacheability attributes but are connected to a non-coherent

      downstream interconnect.



  msi-controller:

    description:

      Only present if the Message Based Interrupt functionality is
@@ -193,6 +199,12 @@ patternProperties: 
      compatible:

        const: arm,gic-v3-its



      dma-noncoherent:

        description:

          Present if the GIC ITS permits programming shareability and

          cacheability attributes but is connected to a non-coherent

          downstream interconnect.



      msi-controller: true



      "#msi-cells":