Commit 5e46ad83 authored by Konrad Dybcio's avatar Konrad Dybcio Committed by Rob Clark
Browse files

drm/msm/a6xx: Ensure clean GMU state in a6xx_gmu_fw_start 



While it's not very well understood, there is some sort of a fault
handler implemented in the GMU firmware which triggers when a certain
bit is set, resulting in the M3 core not booting up the way we expect
it to.

Write a magic value to a magic register to hopefully prevent that
from happening.

Signed-off-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/543335/


Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent 29af7605

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

+6 −0
Original line number Diff line number Diff line
@@ -790,6 +790,12 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) 
	gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_RANGE_0,

		(1 << 31) | (0xa << 18) | (0xa0));



	/*

	 * Snapshots toggle the NMI bit which will result in a jump to the NMI

	 * handler instead of __main. Set the M3 config value to avoid that.

	 */

	gmu_write(gmu, REG_A6XX_GMU_CM3_CFG, 0x4052);



	/*

	 * Note that the GMU has a slightly different layout for

	 * chip_id, for whatever reason, so a bit of massaging