Commit 5e352e32 authored by Fei Yang's avatar Fei Yang Committed by Andi Shyti
Browse files

drm/i915: preparation for using PAT index 



This patch is a preparation for replacing enum i915_cache_level with PAT
index. Caching policy for buffer objects is set through the PAT index in
PTE, the old i915_cache_level is not sufficient to represent all caching
modes supported by the hardware.

Preparing the transition by adding some platform dependent data structures
and helper functions to translate the cache_level to pat_index.

cachelevel_to_pat: a platform dependent array mapping cache_level to
                   pat_index.

max_pat_index: the maximum PAT index recommended in hardware specification
               Needed for validating the PAT index passed in from user
               space.

i915_gem_get_pat_index: function to convert cache_level to PAT index.

obj_to_i915(obj): macro moved to header file for wider usage.

I915_MAX_CACHE_LEVEL: upper bound of i915_cache_level for the
                      convenience of coding.

Cc: Chris Wilson <chris.p.wilson@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarFei Yang <fei.yang@intel.com>
Reviewed-by: default avatarAndi Shyti <andi.shyti@linux.intel.com>
Reviewed-by: default avatarAndrzej Hajda <andrzej.hajda@intel.com>
Signed-off-by: default avatarAndi Shyti <andi.shyti@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230509165200.1740-2-fei.yang@intel.com
parent 5b8ff071

drivers/gpu/drm/i915/gem/i915_gem_object.c

+9 −0
Original line number Diff line number Diff line
@@ -45,6 +45,15 @@ static struct kmem_cache *slab_objects; 


static const struct drm_gem_object_funcs i915_gem_object_funcs;



unsigned int i915_gem_get_pat_index(struct drm_i915_private *i915,

				    enum i915_cache_level level)

{

	if (drm_WARN_ON(&i915->drm, level >= I915_MAX_CACHE_LEVEL))

		return 0;



	return INTEL_INFO(i915)->cachelevel_to_pat[level];

}



struct drm_i915_gem_object *i915_gem_object_alloc(void)

{

	struct drm_i915_gem_object *obj;

drivers/gpu/drm/i915/gem/i915_gem_object.h

+4 −0
Original line number Diff line number Diff line
@@ -20,6 +20,8 @@ 


enum intel_region_id;



#define obj_to_i915(obj__) to_i915((obj__)->base.dev)



static inline bool i915_gem_object_size_2big(u64 size)

{

	struct drm_i915_gem_object *obj;
@@ -30,6 +32,8 @@ static inline bool i915_gem_object_size_2big(u64 size) 
	return false;

}



unsigned int i915_gem_get_pat_index(struct drm_i915_private *i915,

				    enum i915_cache_level level);

void i915_gem_init__objects(struct drm_i915_private *i915);



void i915_objects_module_exit(void);

drivers/gpu/drm/i915/gem/i915_gem_object_types.h

+7 −0
Original line number Diff line number Diff line
@@ -194,6 +194,13 @@ enum i915_cache_level { 
	 * engine.

	 */

	I915_CACHE_WT,

	/**

	 * @I915_MAX_CACHE_LEVEL:

	 *

	 * Mark the last entry in the enum. Used for defining cachelevel_to_pat

	 * array for cache_level to pat translation table.

	 */

	I915_MAX_CACHE_LEVEL,

};



enum i915_map_type {

drivers/gpu/drm/i915/gem/i915_gem_shrinker.c

+0 −2
Original line number Diff line number Diff line
@@ -460,8 +460,6 @@ void i915_gem_shrinker_taints_mutex(struct drm_i915_private *i915, 
	fs_reclaim_release(GFP_KERNEL);

}



#define obj_to_i915(obj__) to_i915((obj__)->base.dev)



/**

 * i915_gem_object_make_unshrinkable - Hide the object from the shrinker. By

 * default all object types that support shrinking(see IS_SHRINKABLE), will also

drivers/gpu/drm/i915/gt/gen8_ppgtt.c

+6 −0
Original line number Diff line number Diff line
@@ -78,6 +78,12 @@ static u64 mtl_pte_encode(dma_addr_t addr, 
	case I915_CACHE_WT:

		pte |= GEN12_PPGTT_PTE_PAT0;

		break;

	default:

		/* This should never happen. Added to deal with the compile

		 * error due to the addition of I915_MAX_CACHE_LEVEL. Will

		 * be removed by the pat_index patch.

		 */

		break;

	}



	return pte;