Commit 5db9d065 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/gmc10.0: convert to IP version checking 



Use IP versions rather than asic_type to differentiate
IP version specific features.

v2: squash in gmc fixes
v3: rebase

Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent eb4fd29a

drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c

+30 −61
Original line number Diff line number Diff line
@@ -133,7 +133,7 @@ static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev, 
		 * the new fast GRBM interface.

		 */

		if ((entry->vmid_src == AMDGPU_GFXHUB_0) &&

		    (adev->asic_type < CHIP_SIENNA_CICHLID))

		    (adev->ip_versions[GC_HWIP] < IP_VERSION(10, 3, 0)))

			RREG32(hub->vm_l2_pro_fault_status);



		status = RREG32(hub->vm_l2_pro_fault_status);
@@ -268,7 +268,7 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, 
	 * to avoid a false ACK due to the new fast GRBM interface.

	 */

	if ((vmhub == AMDGPU_GFXHUB_0) &&

	    (adev->asic_type < CHIP_SIENNA_CICHLID))

	    (adev->ip_versions[GC_HWIP] < IP_VERSION(10, 3, 0)))

		RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req +

				  hub->eng_distance * eng, hub_ip);
@@ -657,8 +657,8 @@ static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev) 


static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev)

{

	switch (adev->asic_type) {

	case CHIP_SIENNA_CICHLID:

	switch (adev->ip_versions[UMC_HWIP]) {

	case IP_VERSION(8, 7, 0):

		adev->umc.max_ras_err_cnt_per_query = UMC_V8_7_TOTAL_CHANNEL_NUM;

		adev->umc.channel_inst_num = UMC_V8_7_CHANNEL_INSTANCE_NUM;

		adev->umc.umc_inst_num = UMC_V8_7_UMC_INSTANCE_NUM;
@@ -674,9 +674,9 @@ static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev) 


static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev)

{

	switch (adev->asic_type) {

	case CHIP_VANGOGH:

	case CHIP_YELLOW_CARP:

	switch (adev->ip_versions[MMHUB_HWIP]) {

	case IP_VERSION(2, 3, 0):

	case IP_VERSION(2, 4, 0):

		adev->mmhub.funcs = &mmhub_v2_3_funcs;

		break;

	default:
@@ -687,13 +687,13 @@ static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev) 


static void gmc_v10_0_set_gfxhub_funcs(struct amdgpu_device *adev)

{

	switch (adev->asic_type) {

	case CHIP_SIENNA_CICHLID:

	case CHIP_NAVY_FLOUNDER:

	case CHIP_VANGOGH:

	case CHIP_DIMGREY_CAVEFISH:

	case CHIP_BEIGE_GOBY:

	case CHIP_YELLOW_CARP:

	switch (adev->ip_versions[GC_HWIP]) {

	case IP_VERSION(10, 3, 0):

	case IP_VERSION(10, 3, 2):

	case IP_VERSION(10, 3, 1):

	case IP_VERSION(10, 3, 4):

	case IP_VERSION(10, 3, 5):

	case IP_VERSION(10, 3, 3):

		adev->gfxhub.funcs = &gfxhub_v2_1_funcs;

		break;

	default:
@@ -800,23 +800,9 @@ static int gmc_v10_0_mc_init(struct amdgpu_device *adev) 
		adev->gmc.visible_vram_size = adev->gmc.real_vram_size;



	/* set the gart size */

	if (amdgpu_gart_size == -1) {

		switch (adev->asic_type) {

		case CHIP_NAVI10:

		case CHIP_NAVI14:

		case CHIP_NAVI12:

		case CHIP_SIENNA_CICHLID:

		case CHIP_NAVY_FLOUNDER:

		case CHIP_VANGOGH:

		case CHIP_DIMGREY_CAVEFISH:

		case CHIP_BEIGE_GOBY:

		case CHIP_YELLOW_CARP:

		case CHIP_CYAN_SKILLFISH:

		default:

	if (amdgpu_gart_size == -1)

		adev->gmc.gart_size = 512ULL << 20;

			break;

		}

	} else

	else

		adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;



	gmc_v10_0_vram_gtt_location(adev, &adev->gmc);
@@ -871,17 +857,17 @@ static int gmc_v10_0_sw_init(void *handle) 
		adev->gmc.vram_vendor = vram_vendor;

	}



	switch (adev->asic_type) {

	case CHIP_NAVI10:

	case CHIP_NAVI14:

	case CHIP_NAVI12:

	case CHIP_SIENNA_CICHLID:

	case CHIP_NAVY_FLOUNDER:

	case CHIP_VANGOGH:

	case CHIP_DIMGREY_CAVEFISH:

	case CHIP_BEIGE_GOBY:

	case CHIP_YELLOW_CARP:

	case CHIP_CYAN_SKILLFISH:

	switch (adev->ip_versions[GC_HWIP]) {

	case IP_VERSION(10, 1, 10):

	case IP_VERSION(10, 1, 1):

	case IP_VERSION(10, 1, 2):

	case IP_VERSION(10, 1, 3):

	case IP_VERSION(10, 3, 0):

	case IP_VERSION(10, 3, 2):

	case IP_VERSION(10, 3, 1):

	case IP_VERSION(10, 3, 4):

	case IP_VERSION(10, 3, 5):

	case IP_VERSION(10, 3, 3):

		adev->num_vmhubs = 2;

		/*

		 * To fulfill 4-level page support,
@@ -989,21 +975,6 @@ static int gmc_v10_0_sw_fini(void *handle) 


static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev)

{

	switch (adev->asic_type) {

	case CHIP_NAVI10:

	case CHIP_NAVI14:

	case CHIP_NAVI12:

	case CHIP_SIENNA_CICHLID:

	case CHIP_NAVY_FLOUNDER:

	case CHIP_VANGOGH:

	case CHIP_DIMGREY_CAVEFISH:

	case CHIP_BEIGE_GOBY:

	case CHIP_YELLOW_CARP:

	case CHIP_CYAN_SKILLFISH:

		break;

	default:

		break;

	}

}



/**
@@ -1162,8 +1133,7 @@ static int gmc_v10_0_set_clockgating_state(void *handle, 
	if (r)

		return r;



	if (adev->asic_type >= CHIP_SIENNA_CICHLID &&

	    adev->asic_type <= CHIP_YELLOW_CARP)

	if (adev->ip_versions[ATHUB_HWIP] >= IP_VERSION(2, 1, 0))

		return athub_v2_1_set_clockgating(adev, state);

	else

		return athub_v2_0_set_clockgating(adev, state);
@@ -1175,8 +1145,7 @@ static void gmc_v10_0_get_clockgating_state(void *handle, u32 *flags) 


	adev->mmhub.funcs->get_clockgating(adev, flags);



	if (adev->asic_type >= CHIP_SIENNA_CICHLID &&

	    adev->asic_type <= CHIP_YELLOW_CARP)

	if (adev->ip_versions[ATHUB_HWIP] >= IP_VERSION(2, 1, 0))

		athub_v2_1_get_clockgating(adev, flags);

	else

		athub_v2_0_get_clockgating(adev, flags);