Commit 5dae69a9 authored by Lucas De Marchi's avatar Lucas De Marchi
Browse files

drm/i915: remove GRAPHICS_VER == 10 



Replace all remaining handling of GRAPHICS_VER {==,>=} 10 with
{==,>=} 11. With the removal of CNL, there is no platform with graphics
version equals 10.

Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210728215946.1573015-24-lucas.demarchi@intel.com
parent 4c6b3021

drivers/gpu/drm/i915/gem/i915_gem_stolen.c

+0 −1
Original line number Original line Diff line number Diff line
@@ -447,7 +447,6 @@ static int i915_gem_init_stolen(struct intel_memory_region *mem) 
		break;

		break;

	case 8:

	case 8:

	case 9:

	case 9:

	case 10:

		if (IS_LP(i915))

		if (IS_LP(i915))

			chv_get_stolen_reserved(i915, uncore,

			chv_get_stolen_reserved(i915, uncore,

						&reserved_base, &reserved_size);

						&reserved_base, &reserved_size);

drivers/gpu/drm/i915/gvt/gtt.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -1055,7 +1055,7 @@ static bool vgpu_ips_enabled(struct intel_vgpu *vgpu) 
{

{

	struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;

	struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;





	if (GRAPHICS_VER(dev_priv) == 9 || GRAPHICS_VER(dev_priv) == 10) {

	if (GRAPHICS_VER(dev_priv) == 9) {

		u32 ips = vgpu_vreg_t(vgpu, GEN8_GAMW_ECO_DEV_RW_IA) &

		u32 ips = vgpu_vreg_t(vgpu, GEN8_GAMW_ECO_DEV_RW_IA) &

			GAMW_ECO_ENABLE_64K_IPS_FIELD;

			GAMW_ECO_ENABLE_64K_IPS_FIELD;

drivers/gpu/drm/i915/i915_debugfs.c

+3 −3
Original line number Original line Diff line number Diff line
@@ -538,20 +538,20 @@ static int i915_frequency_info(struct seq_file *m, void *unused) 
		max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :

		max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :

			    rp_state_cap >> 16) & 0xff;

			    rp_state_cap >> 16) & 0xff;

		max_freq *= (IS_GEN9_BC(dev_priv) ||

		max_freq *= (IS_GEN9_BC(dev_priv) ||

			     GRAPHICS_VER(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);

			     GRAPHICS_VER(dev_priv) >= 11 ? GEN9_FREQ_SCALER : 1);

		seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",

		seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",

			   intel_gpu_freq(rps, max_freq));

			   intel_gpu_freq(rps, max_freq));





		max_freq = (rp_state_cap & 0xff00) >> 8;

		max_freq = (rp_state_cap & 0xff00) >> 8;

		max_freq *= (IS_GEN9_BC(dev_priv) ||

		max_freq *= (IS_GEN9_BC(dev_priv) ||

			     GRAPHICS_VER(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);

			     GRAPHICS_VER(dev_priv) >= 11 ? GEN9_FREQ_SCALER : 1);

		seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",

		seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",

			   intel_gpu_freq(rps, max_freq));

			   intel_gpu_freq(rps, max_freq));





		max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :

		max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :

			    rp_state_cap >> 0) & 0xff;

			    rp_state_cap >> 0) & 0xff;

		max_freq *= (IS_GEN9_BC(dev_priv) ||

		max_freq *= (IS_GEN9_BC(dev_priv) ||

			     GRAPHICS_VER(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);

			     GRAPHICS_VER(dev_priv) >= 11 ? GEN9_FREQ_SCALER : 1);

		seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",

		seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",

			   intel_gpu_freq(rps, max_freq));

			   intel_gpu_freq(rps, max_freq));

		seq_printf(m, "Max overclocked frequency: %dMHz\n",

		seq_printf(m, "Max overclocked frequency: %dMHz\n",

drivers/gpu/drm/i915/i915_drv.h

+1 −1
Original line number Original line Diff line number Diff line
@@ -1597,7 +1597,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, 
	 IS_SKL_GT4(dev_priv))

	 IS_SKL_GT4(dev_priv))





#define HAS_GMBUS_IRQ(dev_priv) (GRAPHICS_VER(dev_priv) >= 4)

#define HAS_GMBUS_IRQ(dev_priv) (GRAPHICS_VER(dev_priv) >= 4)

#define HAS_GMBUS_BURST_READ(dev_priv) (GRAPHICS_VER(dev_priv) >= 10 || \

#define HAS_GMBUS_BURST_READ(dev_priv) (GRAPHICS_VER(dev_priv) >= 11 || \

					IS_GEMINILAKE(dev_priv) || \

					IS_GEMINILAKE(dev_priv) || \

					IS_KABYLAKE(dev_priv))

					IS_KABYLAKE(dev_priv))

drivers/gpu/drm/i915/i915_perf.c

+8 −13
Original line number Original line Diff line number Diff line
@@ -1256,7 +1256,6 @@ static int oa_get_render_ctx_id(struct i915_perf_stream *stream) 




	case 8:

	case 8:

	case 9:

	case 9:

	case 10:

		if (intel_engine_uses_guc(ce->engine)) {

		if (intel_engine_uses_guc(ce->engine)) {

			/*

			/*

			 * When using GuC, the context descriptor we write in

			 * When using GuC, the context descriptor we write in
@@ -2580,7 +2579,7 @@ static void gen8_disable_metric_set(struct i915_perf_stream *stream) 
	intel_uncore_rmw(uncore, GDT_CHICKEN_BITS, GT_NOA_ENABLE, 0);

	intel_uncore_rmw(uncore, GDT_CHICKEN_BITS, GT_NOA_ENABLE, 0);

}

}





static void gen10_disable_metric_set(struct i915_perf_stream *stream)

static void gen11_disable_metric_set(struct i915_perf_stream *stream)

{

{

	struct intel_uncore *uncore = stream->uncore;

	struct intel_uncore *uncore = stream->uncore;
@@ -3887,7 +3886,7 @@ static bool gen8_is_valid_mux_addr(struct i915_perf *perf, u32 addr) 
	       REG_IN_RANGE(addr, RPM_CONFIG0, NOA_CONFIG(8));

	       REG_IN_RANGE(addr, RPM_CONFIG0, NOA_CONFIG(8));

}

}





static bool gen10_is_valid_mux_addr(struct i915_perf *perf, u32 addr)

static bool gen11_is_valid_mux_addr(struct i915_perf *perf, u32 addr)

{

{

	return gen8_is_valid_mux_addr(perf, addr) ||

	return gen8_is_valid_mux_addr(perf, addr) ||

	       REG_EQUAL(addr, GEN10_NOA_WRITE_HIGH) ||

	       REG_EQUAL(addr, GEN10_NOA_WRITE_HIGH) ||
@@ -4395,27 +4394,23 @@ void i915_perf_init(struct drm_i915_private *i915) 




				perf->gen8_valid_ctx_bit = BIT(16);

				perf->gen8_valid_ctx_bit = BIT(16);

			}

			}

		} else if (IS_GRAPHICS_VER(i915, 10, 11)) {

		} else if (GRAPHICS_VER(i915) == 11) {

			perf->ops.is_valid_b_counter_reg =

			perf->ops.is_valid_b_counter_reg =

				gen7_is_valid_b_counter_addr;

				gen7_is_valid_b_counter_addr;

			perf->ops.is_valid_mux_reg =

			perf->ops.is_valid_mux_reg =

				gen10_is_valid_mux_addr;

				gen11_is_valid_mux_addr;

			perf->ops.is_valid_flex_reg =

			perf->ops.is_valid_flex_reg =

				gen8_is_valid_flex_addr;

				gen8_is_valid_flex_addr;





			perf->ops.oa_enable = gen8_oa_enable;

			perf->ops.oa_enable = gen8_oa_enable;

			perf->ops.oa_disable = gen8_oa_disable;

			perf->ops.oa_disable = gen8_oa_disable;

			perf->ops.enable_metric_set = gen8_enable_metric_set;

			perf->ops.enable_metric_set = gen8_enable_metric_set;

			perf->ops.disable_metric_set = gen10_disable_metric_set;

			perf->ops.disable_metric_set = gen11_disable_metric_set;

			perf->ops.oa_hw_tail_read = gen8_oa_hw_tail_read;

			perf->ops.oa_hw_tail_read = gen8_oa_hw_tail_read;





			if (GRAPHICS_VER(i915) == 10) {

				perf->ctx_oactxctrl_offset = 0x128;

				perf->ctx_flexeu0_offset = 0x3de;

			} else {

			perf->ctx_oactxctrl_offset = 0x124;

			perf->ctx_oactxctrl_offset = 0x124;

			perf->ctx_flexeu0_offset = 0x78e;

			perf->ctx_flexeu0_offset = 0x78e;

			}



			perf->gen8_valid_ctx_bit = BIT(16);

			perf->gen8_valid_ctx_bit = BIT(16);

		} else if (GRAPHICS_VER(i915) == 12) {

		} else if (GRAPHICS_VER(i915) == 12) {

			perf->ops.is_valid_b_counter_reg =

			perf->ops.is_valid_b_counter_reg =