Commit 5da7075c authored by Chia-Yuan Li's avatar Chia-Yuan Li Committed by Kalle Valo
Browse files

rtw89: add AXIDMA and TX FIFO dump in mac_mem_dump 



The AXIDMA is tx/rx packet transmission between PCIE host
and device, and TX FIFO is MAC TX data.
We dump them to verify that these memory buffers are correct.

Signed-off-by: default avatarChia-Yuan Li <leo.li@realtek.com>
Signed-off-by: default avatarPing-Ke Shih <pkshih@realtek.com>
Reviewed-by: default avatarLarry Finger <Larry.Finger@lwfinger.net>
Signed-off-by: default avatarKalle Valo <kvalo@codeaurora.org>
Link: https://lore.kernel.org/r/20211122021129.4339-1-pkshih@realtek.com
parent 30101812

drivers/net/wireless/realtek/rtw89/debug.c

+5 −0
Original line number Diff line number Diff line
@@ -723,6 +723,7 @@ rtw89_debug_priv_mac_mem_dump_select(struct file *filp, 
}



static const u32 mac_mem_base_addr_table[RTW89_MAC_MEM_MAX] = {

	[RTW89_MAC_MEM_AXIDMA]	        = AXIDMA_BASE_ADDR,

	[RTW89_MAC_MEM_SHARED_BUF]	= SHARED_BUF_BASE_ADDR,

	[RTW89_MAC_MEM_DMAC_TBL]	= DMAC_TBL_BASE_ADDR,

	[RTW89_MAC_MEM_SHCUT_MACHDR]	= SHCUT_MACHDR_BASE_ADDR,
@@ -735,6 +736,10 @@ static const u32 mac_mem_base_addr_table[RTW89_MAC_MEM_MAX] = { 
	[RTW89_MAC_MEM_BA_CAM]		= BA_CAM_BASE_ADDR,

	[RTW89_MAC_MEM_BCN_IE_CAM0]	= BCN_IE_CAM0_BASE_ADDR,

	[RTW89_MAC_MEM_BCN_IE_CAM1]	= BCN_IE_CAM1_BASE_ADDR,

	[RTW89_MAC_MEM_TXD_FIFO_0]	= TXD_FIFO_0_BASE_ADDR,

	[RTW89_MAC_MEM_TXD_FIFO_1]	= TXD_FIFO_1_BASE_ADDR,

	[RTW89_MAC_MEM_TXDATA_FIFO_0]	= TXDATA_FIFO_0_BASE_ADDR,

	[RTW89_MAC_MEM_TXDATA_FIFO_1]	= TXDATA_FIFO_1_BASE_ADDR,

};



static void rtw89_debug_dump_mac_mem(struct seq_file *m,

drivers/net/wireless/realtek/rtw89/mac.h

+10 −0
Original line number Diff line number Diff line
@@ -227,6 +227,7 @@ enum rtw89_mac_dbg_port_sel { 
/* SRAM mem dump */

#define R_AX_INDIR_ACCESS_ENTRY 0x40000



#define	AXIDMA_BASE_ADDR		0x18006000

#define	STA_SCHED_BASE_ADDR		0x18808000

#define	RXPLD_FLTR_CAM_BASE_ADDR	0x18813000

#define	SECURITY_CAM_BASE_ADDR		0x18814000
@@ -240,10 +241,15 @@ enum rtw89_mac_dbg_port_sel { 
#define	DMAC_TBL_BASE_ADDR		0x18800000

#define	SHCUT_MACHDR_BASE_ADDR		0x18800800

#define	BCN_IE_CAM1_BASE_ADDR		0x188A0000

#define	TXD_FIFO_0_BASE_ADDR		0x18856200

#define	TXD_FIFO_1_BASE_ADDR		0x188A1080

#define	TXDATA_FIFO_0_BASE_ADDR		0x18856000

#define	TXDATA_FIFO_1_BASE_ADDR		0x188A1000



#define CCTL_INFO_SIZE		32



enum rtw89_mac_mem_sel {

	RTW89_MAC_MEM_AXIDMA,

	RTW89_MAC_MEM_SHARED_BUF,

	RTW89_MAC_MEM_DMAC_TBL,

	RTW89_MAC_MEM_SHCUT_MACHDR,
@@ -256,6 +262,10 @@ enum rtw89_mac_mem_sel { 
	RTW89_MAC_MEM_BA_CAM,

	RTW89_MAC_MEM_BCN_IE_CAM0,

	RTW89_MAC_MEM_BCN_IE_CAM1,

	RTW89_MAC_MEM_TXD_FIFO_0,

	RTW89_MAC_MEM_TXD_FIFO_1,

	RTW89_MAC_MEM_TXDATA_FIFO_0,

	RTW89_MAC_MEM_TXDATA_FIFO_1,



	/* keep last */

	RTW89_MAC_MEM_LAST,