Commit 5da12895 authored by Jakub Kicinski's avatar Jakub Kicinski
Browse files

Merge branch 'add-cpswxg-sgmii-support-for-j7200-and-j721e' 

Siddharth Vadapalli says:

====================
Add CPSWxG SGMII support for J7200 and J721E

This series adds support to configure the CPSW Ethernet Switch in SGMII
mode, using the am65-cpsw-nuss driver. SGMII mode is supported by the
CPSWxG instances on TI's J7200 and J721E SoCs. Thus, SGMII mode is added
in the list of extra_modes for the appropriate compatibles corresponding
to the aforementioned SoCs.

Additionally, the method of setting the supported interface via struct
"phylink_config" is simplified by converting the IF/ELSE statements to
SWITCH statements.
====================

Link: https://lore.kernel.org/r/20230321111958.2800005-1-s-vadapalli@ti.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents 603c3345 186016da

drivers/net/ethernet/ti/am65-cpsw-nuss.c

+33 −9
Original line number Diff line number Diff line
@@ -76,6 +76,7 @@ 
#define AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2       0x31C



#define AM65_CPSW_SGMII_CONTROL_REG		0x010

#define AM65_CPSW_SGMII_MR_ADV_ABILITY_REG	0x018

#define AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE	BIT(0)



#define AM65_CPSW_CTL_VLAN_AWARE		BIT(1)
@@ -1496,10 +1497,15 @@ static void am65_cpsw_nuss_mac_config(struct phylink_config *config, unsigned in 
	struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave);

	struct am65_cpsw_common *common = port->common;



	if (common->pdata.extra_modes & BIT(state->interface))

	if (common->pdata.extra_modes & BIT(state->interface)) {

		if (state->interface == PHY_INTERFACE_MODE_SGMII)

			writel(ADVERTISE_SGMII,

			       port->sgmii_base + AM65_CPSW_SGMII_MR_ADV_ABILITY_REG);



		writel(AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE,

		       port->sgmii_base + AM65_CPSW_SGMII_CONTROL_REG);

	}

}



static void am65_cpsw_nuss_mac_link_down(struct phylink_config *config, unsigned int mode,

					 phy_interface_t interface)
@@ -1539,6 +1545,8 @@ static void am65_cpsw_nuss_mac_link_up(struct phylink_config *config, struct phy 


	if (speed == SPEED_1000)

		mac_control |= CPSW_SL_CTL_GIG;

	if (interface == PHY_INTERFACE_MODE_SGMII)

		mac_control |= CPSW_SL_CTL_EXT_EN;

	if (speed == SPEED_10 && phy_interface_mode_is_rgmii(interface))

		/* Can be used with in band mode only */

		mac_control |= CPSW_SL_CTL_EXT_EN;
@@ -2143,18 +2151,34 @@ am65_cpsw_nuss_init_port_ndev(struct am65_cpsw_common *common, u32 port_idx) 
	port->slave.phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000FD;

	port->slave.phylink_config.mac_managed_pm = true; /* MAC does PM */



	if (phy_interface_mode_is_rgmii(port->slave.phy_if)) {

	switch (port->slave.phy_if) {

	case PHY_INTERFACE_MODE_RGMII:

	case PHY_INTERFACE_MODE_RGMII_ID:

	case PHY_INTERFACE_MODE_RGMII_RXID:

	case PHY_INTERFACE_MODE_RGMII_TXID:

		phy_interface_set_rgmii(port->slave.phylink_config.supported_interfaces);

	} else if (port->slave.phy_if == PHY_INTERFACE_MODE_RMII) {

		break;



	case PHY_INTERFACE_MODE_RMII:

		__set_bit(PHY_INTERFACE_MODE_RMII,

			  port->slave.phylink_config.supported_interfaces);

	} else if (common->pdata.extra_modes & BIT(port->slave.phy_if)) {

		__set_bit(PHY_INTERFACE_MODE_QSGMII,

		break;



	case PHY_INTERFACE_MODE_QSGMII:

	case PHY_INTERFACE_MODE_SGMII:

		if (common->pdata.extra_modes & BIT(port->slave.phy_if)) {

			__set_bit(port->slave.phy_if,

				  port->slave.phylink_config.supported_interfaces);

		} else {

			dev_err(dev, "selected phy-mode is not supported\n");

			return -EOPNOTSUPP;

		}

		break;



	default:

		dev_err(dev, "selected phy-mode is not supported\n");

		return -EOPNOTSUPP;

	}



	phylink = phylink_create(&port->slave.phylink_config,

				 of_node_to_fwnode(port->slave.phy_node),
@@ -2753,14 +2777,14 @@ static const struct am65_cpsw_pdata j7200_cpswxg_pdata = { 
	.quirks = 0,

	.ale_dev_id = "am64-cpswxg",

	.fdqring_mode = K3_RINGACC_RING_MODE_RING,

	.extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII),

	.extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII),

};



static const struct am65_cpsw_pdata j721e_cpswxg_pdata = {

	.quirks = 0,

	.ale_dev_id = "am64-cpswxg",

	.fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE,

	.extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII),

	.extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII),

};



static const struct of_device_id am65_cpsw_nuss_of_mtable[] = {