Commit 5d95ff84 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'v6.5-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6 

Pull crypto updates from Herbert Xu:
 "API:
   - Add linear akcipher/sig API
   - Add tfm cloning (hmac, cmac)
   - Add statesize to crypto_ahash

  Algorithms:
   - Allow only odd e and restrict value in FIPS mode for RSA
   - Replace LFSR with SHA3-256 in jitter
   - Add interface for gathering of raw entropy in jitter

  Drivers:
   - Fix race on data_avail and actual data in hwrng/virtio
   - Add hash and HMAC support in starfive
   - Add RSA algo support in starfive
   - Add support for PCI device 0x156E in ccp"

* tag 'v6.5-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (85 commits)
  crypto: akcipher - Do not copy dst if it is NULL
  crypto: sig - Fix verify call
  crypto: akcipher - Set request tfm on sync path
  crypto: sm2 - Provide sm2_compute_z_digest when sm2 is disabled
  hwrng: imx-rngc - switch to DEFINE_SIMPLE_DEV_PM_OPS
  hwrng: st - keep clock enabled while hwrng is registered
  hwrng: st - support compile-testing
  hwrng: imx-rngc - fix the timeout for init and self check
  KEYS: asymmetric: Use new crypto interface without scatterlists
  KEYS: asymmetric: Move sm2 code into x509_public_key
  KEYS: Add forward declaration in asymmetric-parser.h
  crypto: sig - Add interface for sign/verify
  crypto: akcipher - Add sync interface without SG lists
  crypto: cipher - On clone do crypto_mod_get()
  crypto: api - Add __crypto_alloc_tfmgfp
  crypto: api - Remove crypto_init_ops()
  crypto: rsa - allow only odd e and restrict value in FIPS mode
  crypto: geniv - Split geniv out of AEAD Kconfig option
  crypto: algboss - Add missing dependency on RNG2
  crypto: starfive - Add RSA algo support
  ...
parents d85a143b 486bfb05

Documentation/ABI/testing/sysfs-driver-qat

+46 −0
Original line number Diff line number Diff line
@@ -27,7 +27,18 @@ Description: (RW) Reports the current configuration of the QAT device. 


		* sym;asym: the device is configured for running crypto

		  services

		* asym;sym: identical to sym;asym

		* dc: the device is configured for running compression services

		* sym: the device is configured for running symmetric crypto

		  services

		* asym: the device is configured for running asymmetric crypto

		  services

		* asym;dc: the device is configured for running asymmetric

		  crypto services and compression services

		* dc;asym: identical to asym;dc

		* sym;dc: the device is configured for running symmetric crypto

		  services and compression services

		* dc;sym: identical to sym;dc



		It is possible to set the configuration only if the device

		is in the `down` state (see /sys/bus/pci/devices/<BDF>/qat/state)
@@ -47,3 +58,38 @@ Description: (RW) Reports the current configuration of the QAT device. 
			dc



		This attribute is only available for qat_4xxx devices.



What:		/sys/bus/pci/devices/<BDF>/qat/pm_idle_enabled

Date:		June 2023

KernelVersion:	6.5

Contact:	qat-linux@intel.com

Description:	(RW) This configuration option provides a way to force the device into remaining in

		the MAX power state.

		If idle support is enabled the device will transition to the `MIN` power state when

		idle, otherwise will stay in the MAX power state.

		Write to the file to enable or disable idle support.



		The values are:



		* 0: idle support is disabled

		* 1: idle support is enabled



		Default value is 1.



		It is possible to set the pm_idle_enabled value only if the device

		is in the `down` state (see /sys/bus/pci/devices/<BDF>/qat/state)



		The following example shows how to change the pm_idle_enabled of

		a device::



			# cat /sys/bus/pci/devices/<BDF>/qat/state

			up

			# cat /sys/bus/pci/devices/<BDF>/qat/pm_idle_enabled

			1

			# echo down > /sys/bus/pci/devices/<BDF>/qat/state

			# echo 0 > /sys/bus/pci/devices/<BDF>/qat/pm_idle_enabled

			# echo up > /sys/bus/pci/devices/<BDF>/qat/state

			# cat /sys/bus/pci/devices/<BDF>/qat/pm_idle_enabled

			0



		This attribute is only available for qat_4xxx devices.

Documentation/devicetree/bindings/crypto/qcom-qce.yaml

+41 −9
Original line number Diff line number Diff line
@@ -24,12 +24,20 @@ properties: 
        deprecated: true

        description: Kept only for ABI backward compatibility



      - items:

          - enum:

              - qcom,ipq4019-qce

              - qcom,sm8150-qce

          - const: qcom,qce



      - items:

          - enum:

              - qcom,ipq6018-qce

              - qcom,ipq8074-qce

              - qcom,msm8996-qce

              - qcom,qcm2290-qce

              - qcom,sdm845-qce

              - qcom,sm6115-qce

          - const: qcom,ipq4019-qce

          - const: qcom,qce
@@ -46,16 +54,12 @@ properties: 
    maxItems: 1



  clocks:

    items:

      - description: iface clocks register interface.

      - description: bus clocks data transfer interface.

      - description: core clocks rest of the crypto block.

    minItems: 1

    maxItems: 3



  clock-names:

    items:

      - const: iface

      - const: bus

      - const: core

    minItems: 1

    maxItems: 3



  iommus:

    minItems: 1
@@ -89,9 +93,37 @@ allOf: 
            enum:

              - qcom,crypto-v5.1

              - qcom,crypto-v5.4

              - qcom,ipq4019-qce

              - qcom,ipq6018-qce

              - qcom,ipq8074-qce

              - qcom,msm8996-qce

              - qcom,sdm845-qce

    then:

      properties:

        clocks:

          maxItems: 3

        clock-names:

          items:

            - const: iface

            - const: bus

            - const: core

      required:

        - clocks

        - clock-names



  - if:

      properties:

        compatible:

          contains:

            enum:

              - qcom,qcm2290-qce

              - qcom,sm6115-qce

    then:

      properties:

        clocks:

          maxItems: 1

        clock-names:

          items:

            - const: core

      required:

        - clocks

        - clock-names

Documentation/devicetree/bindings/crypto/starfive,jh7110-crypto.yaml

0 → 100644
+70 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/crypto/starfive,jh7110-crypto.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: StarFive Cryptographic Module



maintainers:

  - Jia Jie Ho <jiajie.ho@starfivetech.com>

  - William Qiu <william.qiu@starfivetech.com>



properties:

  compatible:

    const: starfive,jh7110-crypto



  reg:

    maxItems: 1



  clocks:

    items:

      - description: Hardware reference clock

      - description: AHB reference clock



  clock-names:

    items:

      - const: hclk

      - const: ahb



  interrupts:

    maxItems: 1



  resets:

    maxItems: 1



  dmas:

    items:

      - description: TX DMA channel

      - description: RX DMA channel



  dma-names:

    items:

      - const: tx

      - const: rx



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - resets

  - dmas

  - dma-names



additionalProperties: false



examples:

  - |

    crypto: crypto@16000000 {

        compatible = "starfive,jh7110-crypto";

        reg = <0x16000000 0x4000>;

        clocks = <&clk 15>, <&clk 16>;

        clock-names = "hclk", "ahb";

        interrupts = <28>;

        resets = <&reset 3>;

        dmas = <&dma 1 2>,

               <&dma 0 2>;

        dma-names = "tx", "rx";

    };

...

MAINTAINERS

+7 −0
Original line number Diff line number Diff line
@@ -20265,6 +20265,13 @@ F: Documentation/devicetree/bindings/clock/starfive,jh71*.yaml 
F:	drivers/clk/starfive/clk-starfive-jh71*

F:	include/dt-bindings/clock/starfive?jh71*.h









STARFIVE CRYPTO DRIVER









M:	Jia Jie Ho <jiajie.ho@starfivetech.com>









M:	William Qiu <william.qiu@starfivetech.com>









S:	Supported









F:	Documentation/devicetree/bindings/crypto/starfive*









F:	drivers/crypto/starfive/

















STARFIVE JH71X0 PINCTRL DRIVERS









M:	Emil Renner Berthing <kernel@esmil.dk>









M:	Jianlong Huang <jianlong.huang@starfivetech.com>

























arch/arm/crypto/sha1_neon_glue.c



+5
−7






























Original line number
Diff line number
Diff line







@@ -26,8 +26,8 @@

















#include "sha1.h"



















asmlinkage void sha1_transform_neon(void *state_h, const char *data,









				    unsigned int rounds);









asmlinkage void sha1_transform_neon(struct sha1_state *state_h,









				    const u8 *data, int rounds);



















static int sha1_neon_update(struct shash_desc *desc, const u8 *data,









			  unsigned int len)








@@ -39,8 +39,7 @@ static int sha1_neon_update(struct shash_desc *desc, const u8 *data,







		return sha1_update_arm(desc, data, len);



















	kernel_neon_begin();









	sha1_base_do_update(desc, data, len,









			    (sha1_block_fn *)sha1_transform_neon);









	sha1_base_do_update(desc, data, len, sha1_transform_neon);









	kernel_neon_end();



















	return 0;








@@ -54,9 +53,8 @@ static int sha1_neon_finup(struct shash_desc *desc, const u8 *data,

















	kernel_neon_begin();









	if (len)









		sha1_base_do_update(desc, data, len,









				    (sha1_block_fn *)sha1_transform_neon);









	sha1_base_do_finalize(desc, (sha1_block_fn *)sha1_transform_neon);









		sha1_base_do_update(desc, data, len, sha1_transform_neon);









	sha1_base_do_finalize(desc, sha1_transform_neon);









	kernel_neon_end();



















	return sha1_base_finish(desc, out);