Commit 5d934ac0 authored Oct 04, 2019 by Alex Deucher

drm/amdgpu: add new SMU 7.1.3 registers for BACO



Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

parent 9fc00ea7

drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -52,6 +52,7 @@
		#define ixCG_SPLL_FUNC_CNTL_5 0xc0500150
		#define ixCG_SPLL_FUNC_CNTL_6 0xc0500154
		#define ixCG_SPLL_FUNC_CNTL_7 0xc0500158
		#define ixCG_SPLL_STATUS 0xC050015C
		#define ixSPLL_CNTL_MODE 0xc0500160
		#define ixCG_SPLL_SPREAD_SPECTRUM 0xc0500164
		#define ixCG_SPLL_SPREAD_SPECTRUM_2 0xc0500168

drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h

+2 −0

Original line number	Diff line number	Diff line
		@@ -220,6 +220,8 @@
		#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR__SHIFT 0x19
		#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL_MASK 0xfff
		#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL__SHIFT 0x0
		#define CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK 0x2
		#define CG_SPLL_STATUS__SPLL_CHG_STATUS__SHIFT 0x1
		#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1
		#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL__SHIFT 0x0
		#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV_MASK 0x2